Virtual Bus FPGA Agents for Autonomous Vehicle Connectivity
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Solution Overview
Problem
Existing distributed computing systems in autonomous driving vehicles face challenges with complex wiring, low data transfer efficiency, and difficulty in preserving precise time information due to the use of multiple bus interfaces, which complicates deployment and error diagnosis.
Innovation Solution
A distributed computing system with a universal virtual bus structure using high-speed serial physical links and FPGA agents for uniform system-to-system connectivity, enabling efficient data transfer and synchronization without extra synchronization channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple bus interfaces (Ethernet, PCIe, SPI, I2C, UART) are used for system-to-system connectivity, then adaptability to different devices is improved, but device complexity and board space increase
Solution Approach 1:
The patent implements a universal virtual bus architecture where a single high-speed serial bus interface can handle multiple communication protocols and data types. The FPGA-based virtual bus controller can dynamically configure the interface to support different communication modes (Ethernet, PCIe, SPI, I2C, UART) over the same physical connection, eliminating the need for multiple dedicated interfaces and reducing board space while maintaining adaptability to various devices
Solution Approach 2:
The patent introduces a virtual bus controller based on FPGA as an intermediary layer between the main compute system and various subsystems. This mediator translates and manages communications between different protocols over a unified high-speed serial bus, allowing devices with different interface requirements to communicate through a single standardized connection, thereby reducing wiring complexity while preserving device compatibility
2Adaptability or versatility
If multiple bus interfaces are used for system-to-system connectivity, then adaptability to different devices is improved, but ease of deployment and error diagnosis worsen
Solution Approach 1:
By implementing a universal virtual bus that can dynamically adapt to different communication protocols, the system simplifies deployment procedures. The unified interface requires only a single connection setup rather than multiple interface configurations, and error diagnosis is improved because all communications flow through a single standardized pathway, making troubleshooting more systematic and less complex
3Device complexity
If Ethernet-only interface design is used, then device complexity is reduced, but data transfer efficiency for large raw sensor data deteriorates
Solution Approach 1:
The patent employs a high-speed serial bus interface with configurable parameters that can be dynamically adjusted based on data requirements. For large raw sensor data, the interface operates in high-bandwidth mode with optimized serialization parameters, while for control signals it switches to protocol-specific modes. This parameter flexibility maintains simplicity by using a single interface type while achieving data transfer efficiencies comparable to or exceeding dedicated multi-interface designs
4Device complexity
If Ethernet-only interface design is used, then device complexity is reduced, but ability to preserve precise time information for synchronization deteriorates
Solution Approach 1:
The virtual bus controller can dynamically change operational parameters to include precise timing and synchronization modes when needed. The high-speed serial interface supports configurable clocking schemes and timestamping capabilities that can be activated for subsystems requiring precise time information, while maintaining simpler operation for other devices. This allows the single interface to provide both simplicity and precise time preservation as required by different subsystems
Data Source
AI summary
A distributed computing system in an autonomous driving vehicle (ADV) includes a main compute system and multiple subsystems, and a bus structure that connect the main compute system and the multiple subsystems. The bus structure provides uniform system-to-system connectivity. A host field-programmable gate array (FPGA) agent coupled to the main compute system can communicate with slave FPGA agents on the subsystems via multiple pairs of bus interface protocols of a particular type. The bus interfaces on the FPGA agents supports the uniform system-to-system connectivity.