Virtual Bus Model for Concurrent Transaction Simulation

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Solution Overview

Problem

There is a need for efficient simulation methods that can accurately model complex bus structures and their connections to interconnect circuits, particularly in system designs incorporating programmable processors, as existing methods struggle with handling concurrent transactions and complex behaviors in modern bus protocols like the AXI protocol.

Innovation Solution

A customizable virtual bus model that allows for concurrent read and write operations without arbitration, using separate read and write ports, and implements dynamic transaction event stitching, automatic bus routing, and synchronization mechanisms to handle multiple simultaneous transactions and master devices, enabling efficient data transfer and simulation performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional bus simulation methods are used, then simulation accuracy can be maintained, but simulation performance and speed deteriorate due to inability to handle concurrent transactions efficiently

Engineering Contradiction:
Improvesimulation performanceVSAvoidsimulation accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The bus model is segmented into separate read ports and write ports, allowing independent handling of read and write transactions. This segmentation enables concurrent processing of multiple transactions without arbitration, significantly improving simulation performance while maintaining accuracy through dedicated transaction paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bus model dynamically adjusts its behavior based on transaction types and timing. The model supports flexible transaction ordering and timing relationships, allowing it to adapt to different bus protocols and simulation scenarios while maintaining accurate behavioral modeling.

Inventive Principle:
Principle #15Dynamics

2Reliability

If complex bus protocols like AXI are simulated with full detail, then simulation accuracy improves, but device complexity and simulation overhead increase

Engineering Contradiction:
Improvesimulation accuracyVSAvoidbus model complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention creates virtual copies of bus interfaces and transaction models that replicate the behavior of complex protocols like AXI without requiring full implementation of all protocol details. These virtual models capture essential behavioral characteristics while simplifying the simulation overhead.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The bus model is designed with universal interfaces that can handle multiple bus protocols through configuration rather than separate implementations. The same core model structure supports different protocols by adjusting parameters and transaction handling rules, reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Stability of the object's composition

If arbitration mechanisms are implemented for bus access, then transaction ordering is controlled, but simulation speed decreases due to additional synchronization overhead

Engineering Contradiction:
Improvetransaction orderingVSAvoidsimulation speed
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

By separating read and write transactions into distinct ports with independent processing paths, the model eliminates the need for centralized arbitration. Each port handles its transaction type independently, maintaining proper ordering within each category while removing arbitration overhead that would slow down simulation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10409935B2Modeling a bus for a system design incorporating one or more programmable processors
Publication Date: 2019.09.10 SYNOPSYS INC
  • US10409935B2 patent drawing
  • US10409935B2 patent drawing
  • US10409935B2 patent drawing

AI summary

Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.