Virtual Bus Model for Concurrent Transaction Simulation
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Solution Overview
Problem
There is a need for efficient simulation methods that can accurately model complex bus structures and their interactions within system-on-chip (SoC) designs, particularly for systems with custom programmable processors, as existing methods struggle with the complexity and variability of modern electronic circuits.
Innovation Solution
A customizable virtual bus model that allows concurrent read and write operations without arbitration, conforming to the AXI protocol, and includes dynamic transaction event stitching and automatic bus routing, enabling simulation of multiple simultaneous transactions and supporting various bus protocols like AXI, AHB, and PCI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional bus simulation methods are used, then simulation accuracy is maintained, but simulation performance deteriorates due to the complexity of modern bus structures and multiple simultaneous transactions
Solution Approach 1:
The bus simulation model is segmented into multiple independent transaction channels, each capable of handling simultaneous transactions. This segmentation allows the simulation to process multiple transactions in parallel without requiring complex arbitration logic, thereby improving simulation performance while maintaining accuracy.
Solution Approach 2:
The simulation model performs preliminary actions by pre-establishing transaction channels and routing paths before actual transactions occur. This allows the system to handle multiple simultaneous transactions efficiently without requiring complex real-time arbitration, thus improving simulation performance.
2Reliability
If arbitration logic is implemented for bus access, then transaction ordering is ensured, but simulation performance deteriorates due to the overhead of arbitration operations
Solution Approach 1:
The bus model is divided into separate read and write channels, each with its own transaction queue. This segmentation eliminates the need for complex arbitration logic while ensuring proper transaction ordering within each channel, thereby maintaining reliability without sacrificing simulation performance.
Solution Approach 2:
The simulation model dynamically assigns transactions to appropriate channels based on their type (read or write) and processes them independently. This dynamic approach ensures proper ordering without requiring static arbitration logic, improving simulation performance while maintaining transaction reliability.
3Measurement precision
If detailed virtual bus models are created for custom processors, then simulation accuracy is improved, but model design complexity increases
Solution Approach 1:
The virtual bus model is designed with universal components that can be configured to support multiple bus protocols (AXI, AHB, PCI) and custom processor requirements. This multi-functionality allows the same base model to be adapted for different applications, improving simulation accuracy without proportionally increasing model design complexity.
Solution Approach 2:
The bus model uses configurable parameters to adapt to different protocol requirements and custom processor specifications. By changing parameters rather than redesigning the entire model, the system achieves high simulation accuracy for custom processors while keeping model design complexity manageable.
Data Source
AI summary
Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.