Virtual Cache Directory Eliminates TLB Lookup
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Solution Overview
Problem
The increasing size of microprocessor core caches leads to power consumption issues and timing constraints in Translation Lookaside Buffers (TLBs), which are critical in translating virtual to physical addresses, resulting in inefficiencies in cache memory access.
Innovation Solution
Implementing a virtual cache directory with a logically indexed and logically tagged structure that eliminates the need for TLB lookup during L1 cache hits, using a set-associative cache with a vertically stacked validation directory to reduce power consumption and improve access times, and integrating a TLB and higher-level cache for cache misses to confirm validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If TLB is used to translate logical addresses to physical addresses in cache memory access, then address translation is achieved, but power consumption increases and access time increases
Solution Approach 1:
The patent extracts the address translation function from the TLB and relocates it to the cache directory. The cache directory now contains both logical addresses and physical addresses, allowing translation to occur during cache lookup without requiring a separate TLB access. This eliminates the need for TLB power-up during cache hits, directly reducing power consumption while maintaining accurate address translation.
Solution Approach 2:
The patent merges the address translation functionality with the cache directory structure. By storing both logical and physical addresses in the same directory entry and performing translation during the cache lookup process, the invention combines two previously separate operations (TLB translation and cache lookup) into a single unified operation, reducing both power consumption and access time.
2Quantity of substance
If TLB size is increased to handle growing cache memory, then address translation capacity improves, but timing constraints are violated and power consumption increases
Solution Approach 1:
The patent extracts the address translation function from the TLB and relocates it to the cache directory. The cache directory now contains both logical addresses and physical addresses, allowing translation to occur during cache lookup without requiring a separate TLB access. This eliminates the need for TLB power-up during cache hits, directly reducing power consumption while maintaining accurate address translation.
Solution Approach 2:
The patent merges the address translation functionality with the cache directory structure. By storing both logical and physical addresses in the same directory entry and performing translation during the cache lookup process, the invention combines two previously separate operations (TLB translation and cache lookup) into a single unified operation, reducing both power consumption and access time.
3Measurement precision
If separate TLB lookup and cache directory lookup are performed, then address translation is complete, but access time increases due to critical path delays
Solution Approach 1:
The patent merges the address translation functionality with the cache directory structure. By storing both logical and physical addresses in the same directory entry and performing translation during the cache lookup process, the invention combines two previously separate operations (TLB translation and cache lookup) into a single unified operation, reducing both power consumption and access time.
Solution Approach 2:
The patent performs address translation in advance by pre-loading both logical and physical addresses into the cache directory entries before they are needed. This preliminary action allows the translation to be completed as part of the cache lookup process itself, rather than requiring a separate subsequent TLB access, thereby reducing the critical path delay.
Data Source
AI summary
Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.