Virtual Address Cache Invalidation via Physical Mapping
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Solution Overview
Problem
Existing data processing systems face inefficiencies in cache invalidation due to the use of physical addresses, which can lead to unnecessary invalidation of entries when virtual addresses are not directly indexed, resulting in performance penalties.
Innovation Solution
A data processing apparatus and method that utilizes a cache indexed by virtual addresses, with a correspondence table to map physical addresses to virtual addresses, allowing for precise invalidation of cache entries based on physical addresses in incoming invalidation requests, thereby maintaining coherency without incurring the performance penalty of invalidating all entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the cache is indexed by virtual addresses, then the need for virtual-to-physical address conversion is eliminated, improving access speed, but invalidation requests using physical addresses cannot directly invalidate the corresponding virtual address entries
Solution Approach 1:
The patent introduces a correspondence table as an intermediary data structure that maps physical addresses to virtual addresses. When an invalidation request with a physical address is received, the system uses this correspondence table to find the corresponding virtual address, then invalidates the correct cache entry. This mediator resolves the mismatch between the virtual-addressed cache and physical-addressed invalidation requests.
2Reliability
If invalidation requests use physical addresses, then all virtual addresses mapping to the same physical address can be invalidated, ensuring coherency, but this requires additional address translation overhead
Solution Approach 1:
The system performs preliminary action by pre-establishing the correspondence between physical and virtual addresses in a correspondence table before invalidation is needed. This table is populated in advance during normal cache operations, so when an invalidation request arrives, the translation can proceed quickly without full address translation overhead, thus maintaining coherency while minimizing time loss.
3Reliability
If all cache entries are invalidated upon receiving an invalidation request, then coherency is maintained, but performance penalty increases due to unnecessary invalidation of unrelated entries
Solution Approach 1:
The patent applies local quality by making the invalidation operation localized and precise. Instead of invalidating all cache entries globally, the system uses the correspondence table to identify only the specific virtual address entries that correspond to the requested physical address, and invalidates only those local entries. This maintains coherency where needed while preserving performance by leaving other cache entries intact.
Data Source
AI summary
A data processing apparatus is provided, which includes a cache to store operations produced by decoding instructions fetched from memory. The cache is indexed by virtual addresses of the instructions in the memory. Receiving circuitry receives an incoming invalidation request that references a physical address in the memory. Invalidation circuitry invalidates entries in the cache where the virtual address corresponds with the physical address. Coherency is thereby achieved when using a cache that is indexed using virtual addresses.