Virtual Cache Checkpointing for Memory Expansion

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Solution Overview

Problem

Conventional cache memory management systems face limitations in expanding memory capacity and reducing underlying memory consumption, leading to increased latency due to the finite and expensive nature of cache memory, especially in scenarios with frequent and random data transactions.

Innovation Solution

A method and system that utilize a virtual cache architecture to segregate datasets into data blocks, identify checkpoints based on frequency and association, and recall sequences from main memory for execution, thereby efficiently managing cache memory and reducing memory consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional cache memory is used, then fast data access is achieved, but memory capacity is limited and expensive

Engineering Contradiction:
Improvedata access speedVSAvoidmemory capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The cache memory is segmented into multiple levels (L1, L2, L3) with different capacities and access speeds. The system divides the cache into valid and invalid portions, and further segments data into data blocks that can be independently managed and replaced, allowing efficient use of limited cache space while maintaining fast access for frequently used data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to cache memory management by adding multiple cache levels (L1, L2, L3) with increasing capacity and decreasing access speed. This dimensional expansion allows the system to maintain fast access for hot data in smaller caches while providing larger capacity in deeper cache levels, effectively resolving the capacity-speed tradeoff.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of time

If cache memory size is increased to handle frequent random data transactions, then latency is reduced, but cost increases

Engineering Contradiction:
Improvedata transaction latencyVSAvoidcache memory size
Core Design Contradiction:
Loss of timeVSQuantity of substance

Solution Approach 1:

Different portions of the cache memory are assigned different qualities and functions. The L1 cache provides fastest access for most frequently accessed data, L2 provides medium-speed access for less frequent data, and L3 provides larger capacity for even less frequent data. This local quality differentiation allows the system to optimize for speed where needed while using capacity where appropriate, reducing overall latency without requiring uniformly high-quality (expensive) memory throughout.

Inventive Principle:
Principle #3Local quality

3Quantity of substance

If virtual cache is implemented to expand memory, then cache capacity is increased, but underlying memory consumption increases in the same manner as conventional cache

Engineering Contradiction:
Improvevirtual cache capacityVSAvoidunderlying memory consumption
Core Design Contradiction:
Quantity of substanceVSLoss of substance

Solution Approach 1:

The system implements a least recently used (LRU) replacement policy that discards invalid or least frequently accessed data blocks from the cache when space is needed. The cache management unit tracks which data blocks are valid and which are invalid, allowing it to efficiently discard outdated data and recover cache space for new or frequently accessed data, thereby expanding effective cache capacity without proportionally increasing underlying memory consumption.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS11520702B2System and method for managing cache memory
Publication Date: 2022.12.06 WIPRO LTD
  • US11520702B2 patent drawing
  • US11520702B2 patent drawing
  • US11520702B2 patent drawing

AI summary

The present invention discloses a method and a system for managing cache memory. The system comprising a processor is configured to receive datasets from one or more applications, segregate the received datasets into one or more data blocks, identify a checkpoint from previously created checkpoints stored in a virtual cache corresponding to the one or more data blocks, wherein the checkpoints are previously created based on frequency of repetition of each of the one or more data blocks and association between the each of the one or more data blocks, recall a sequence of previously stored data blocks from main memory based on the identified checkpoint, and send the sequence of previously stored data blocks to the one or more applications for execution, thereby managing cache memory.