Virtual Cache Snoop Filter for Heterogeneous Coherency
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Solution Overview
Problem
Current methods for achieving full cache coherency in heterogeneous computing, particularly with graphics processing units and digital signal processors, incur increased latency, constrained bandwidth, and complexity due to the need for a memory management unit on the critical path to lowest level caches, often resulting in unnecessary cache line invalidations.
Innovation Solution
Implementing a snoop filter to manage snoops and cache coherency operations for a virtual cache, which determines whether snooped lines are in the virtual cache and only sends coherency operations when necessary, thereby reducing the need for a memory management unit on the critical path and avoiding unnecessary cache line replacements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory management unit is placed on the critical path to the lowest level caches to provide full cache coherency, then cache coherency is achieved, but latency increases and bandwidth is constrained
Solution Approach 1:
The patent extracts the MMU from the critical path by introducing a virtual cache layer. The virtual cache handles coherency operations independently using virtual addresses, removing the bottleneck that previously required MMU intervention for every cache access. This separation allows the critical path to operate without MMU overhead while coherency is maintained through the virtual cache's address translation and snoop filtering mechanisms.
Solution Approach 2:
The virtual cache acts as an intermediary between the coherent processing devices and the physical caches. It mediates coherency operations by translating virtual addresses to physical addresses and filtering snoops before they reach the physical caches. This intermediary layer eliminates the need for MMU involvement in the critical path while maintaining full coherency across heterogeneous devices.
2Reliability
If a memory management unit is placed on the critical path to provide full cache coherency, then cache coherency is achieved, but device complexity increases
Solution Approach 1:
The patent removes the MMU from the coherency management path and replaces it with a virtual cache that handles address translation and coherency filtering. This extraction eliminates the need for complex MMU-coherency integration logic, reducing device complexity while maintaining coherency through the virtual cache's dedicated coherency management structures.
Solution Approach 2:
The system segments coherency management from the main MMU path by creating a dedicated virtual cache layer. This segmentation isolates coherency operations into a separate module that uses its own address translation and filtering mechanisms, reducing the complexity burden on the main MMU and allowing independent optimization of each component.
3Reliability
If a memory management unit is used for cache coherency, then coherency state tracking is achieved, but over-invalidation of cache lines occurs when not required
Solution Approach 1:
The virtual cache implements partial coherency validation by filtering snoops based on virtual address matching. Instead of invalidating all cache lines upon any snoop (excessive action), it selectively validates only those lines that correspond to matching virtual addresses. This partial validation approach maintains coherency where needed while avoiding unnecessary invalidations, improving cache line utilization.
Solution Approach 2:
The virtual cache performs preliminary address translation and snoop filtering before coherency operations reach the physical caches. By pre-processing snoops and translating virtual addresses early in the pipeline, the system can determine in advance which cache lines require validation, preventing premature or unnecessary invalidations and improving overall cache efficiency.
Data Source
AI summary
Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.