Virtual Cache TLB Invalidation Using Load Store Queue Marking

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Solution Overview

Problem

Current methods for Translation Lookaside Buffer (TLB) invalidation in multi-processor systems face inefficiencies due to overmarking, which slows performance by requiring all load/store operations to complete before acknowledging TLB invalidation, especially in systems with many cores, and existing solutions are either costly or impact performance.

Innovation Solution

Implementing a virtual cache that uses virtual addresses to invalidate cache entries and mark pending load/store operations, allowing precise marking without overmarking and maintaining performance, by searching the cache for a matching virtual address and marking corresponding load/store queue entries as pending.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hardware based invalidations are used to invalidate cached page table entries in multi-processor systems, then correctness of TLB invalidation is improved, but system performance deteriorates due to overmarking load/store operations

Engineering Contradiction:

Improvecorrectness of TLB invalidationVSAvoidsystem performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the invalidation process by separating precise cache entry identification from load/store operation marking. Instead of marking all load/store operations conservatively, the system only marks operations that precisely match the invalidated cache entry's set and way, reducing unnecessary markings while maintaining correctness

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the marking criteria from conservative broad marking to precise marking based on specific cache parameters (set and way). By using these parameters to selectively mark only matching load/store operations, the system reduces the number of marked operations from all possible operations to only those that truly need to be held pending

Inventive Principle:

Principle #35Parameter changes

2Reliability

If all load/store operations are marked as pending to ensure correct ordering, then correctness of operation ordering is improved, but acknowledgment time deteriorates

Engineering Contradiction:

Improvecorrect ordering of load/store operationsVSAvoidacknowledgment time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by marking only the necessary subset of load/store operations that match the invalidated cache entry, rather than marking all operations. This selective approach holds only the required operations pending, allowing faster acknowledgment while maintaining correct ordering

Inventive Principle:

Principle #16Partial or excessive action

3Productivity

If precise marking without overmarking is implemented, then system performance is improved, but complexity of tracking cache entries increases

Engineering Contradiction:

Improvesystem performanceVSAvoidcomplexity of tracking cache entries

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary mechanism where the cache entry's set and way parameters serve as the key to selectively identify and mark matching load/store operations. This intermediary approach simplifies tracking by using existing cache parameters rather than requiring complex new tracking infrastructure

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11263151B2Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations

Publication Date: 2022.03.01 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.