Virtual Cell Model for Semiconductor Design Verification
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Solution Overview
Problem
Current semiconductor design verification processes face significant challenges due to the complexity of modern integrated circuits, which require adherence to thousands of design rules and result in high memory requirements and increased processing time, especially as designs grow larger and more complex, leading to inefficiencies in hierarchical DRC methodologies.
Innovation Solution
The implementation of a virtual cell model using virtual hierarchical layers (VHL) allows for efficient single-pass bottom-up hierarchical processing by generating a compressed representation of cell data, reducing memory usage and eliminating the need to load entire design layers into memory, enabling cell-level geometric operations and parallel processing without data flattening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional hierarchical DRC methodologies are used to process large semiconductor designs, then design verification can be performed, but memory requirements increase significantly and processing time increases
Solution Approach 1:
The patent extracts only the necessary geometric data from child cells and stores it in virtual cell models, rather than loading entire design layers into memory. This selective extraction of essential information reduces memory consumption while maintaining verification accuracy.
Solution Approach 2:
The patent segments the design verification process into bottom-up hierarchical stages, processing cells at the lowest level first and progressively moving upward. This segmentation allows memory to be reused across different hierarchy levels, reducing peak memory requirements.
2Reliability
If traditional hierarchical DRC methodologies are used to process large semiconductor designs, then design verification can be performed, but processing time increases
Solution Approach 1:
The patent performs preliminary processing at the child cell level by generating virtual cell models that contain pre-computed geometric information. This preliminary action eliminates the need to reload and reprocess data at parent cell levels, reducing overall processing time.
Solution Approach 2:
The patent maintains continuous processing flow by keeping virtual cell models in memory during the bottom-up traversal, allowing uninterrupted geometric operations without repeated data loading and unloading cycles.
3Loss of information
If entire design layers are loaded into memory for verification, then complete geometric information is available, but memory consumption increases significantly
Solution Approach 1:
The patent extracts only the essential geometric information needed for verification from child cells and stores it in compressed virtual cell models. This selective extraction maintains geometric information completeness for verification purposes while dramatically reducing memory consumption.
Solution Approach 2:
Instead of loading all data into memory and then filtering, the patent inverts the approach by selectively extracting and loading only the necessary geometric information into virtual cell models, achieving both memory efficiency and information completeness.
4Device complexity
If data flattening is used to simplify hierarchical processing, then processing complexity is reduced, but processing time increases significantly
Solution Approach 1:
The patent creates virtual copies of child cell geometric information in the form of virtual cell models that can be efficiently accessed and manipulated. These copies maintain the hierarchical structure benefits while enabling simplified processing operations without the time penalty of full data flattening.
Data Source
AI summary
Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created.