Virtual Channel Interface for FPGA Logic Units
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Solution Overview
Problem
Communication between logic units of different types, such as software applications and HDL entities, in FPGA systems is hindered by varying processing speeds and data sizes, requiring efficient data transfer mechanisms to facilitate effective collaboration and debugging.
Innovation Solution
The implementation of a virtual channel communication system using interface modules with unique identification numbers, allowing for duplex data transfer and a two-sided handshake method to manage data exchange between logic units, decoupling the communication process from the logic units themselves and configuring communication structures during the system configuration phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If direct communication between logic units of different types is implemented, then data transfer capability is improved, but communication reliability deteriorates due to varying processing speeds and data sizes
Solution Approach 1:
The patent introduces a message-based communication interface as an intermediary between logic units of different types. Messages serve as standardized carriers that mediate data exchange, abstracting away the differences in processing speeds and data sizes between software applications and HDL entities. This intermediary layer enables reliable communication by providing a uniform protocol that both types of logic units can understand and process.
2Reliability
If communication protocols are made robust to handle different logic unit types, then communication reliability is improved, but device complexity increases
Solution Approach 1:
The patent employs parameter-based message structures that can be configured to match the specific requirements of different logic unit pairs. Instead of implementing complex conditional logic to handle different unit types, the system changes parameters such as message format, data size, and timing characteristics based on the communicating units' capabilities. This allows a single unified protocol to adapt to various scenarios without increasing overall complexity.
3Reliability
If synchronization mechanisms are added to handle speed differences, then communication reliability is improved, but loss of time increases due to waiting and coordination overhead
Solution Approach 1:
The patent implements preliminary configuration of communication parameters during system initialization or design phase. Timing characteristics, buffer sizes, and data format requirements are predetermined and configured before actual communication begins. This preliminary setup eliminates the need for runtime synchronization and waiting, as each logic unit already knows how to process messages from its partners without requiring coordination during data transfer.
4Ease of operation
If interface modules are introduced to manage communication, then ease of operation is improved, but device complexity increases
Solution Approach 1:
The patent implements universal interface modules that can handle communication with any type of logic unit through a standardized message protocol. These interface modules are multi-functional, serving both software applications and HDL entities without requiring separate specialized interfaces. The universality of the interface modules simplifies operation by providing a consistent programming model while the modular architecture prevents complexity proliferation through code reuse and standardization.
Data Source
AI summary
A communication system includes a first interface module which can be coupled to a first logic unit and a second interface module which can be coupled to a second logic unit. The first and second interface modules are interconnected by a virtual channel over a routing network. The first interface module is configured to receive messages from the first interface module and to send the received messages over the virtual channel to the second interface module. The second interface module is configured to transmit the received messages to the second logic unit. The second interface module is further configured to receive a processing complete signal from the second logic unit when the received messages have been processed in the second logic unit and is further configured to send an acknowledgement signal to the first interface module after reception of the processing complete signal. Further a communication method is provided.