Virtual Channel Packet Reordering for Deadlock Avoidance

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Solution Overview

Problem

Data processing devices face inefficiencies when supporting multiple internal virtual channels due to limited resources on physical communication links, leading to potential communication blockages and inefficiencies in packet handling.

Innovation Solution

The implementation of a method where multiple internal virtual channels are associated with a single link virtual channel, using FIFOs to manage packet storage and flow control, allowing for dynamic reordering and prioritization based on resource availability and packet types, thereby reducing deadlock and optimizing communication flows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If full amount of communication resources are allocated to each single virtual channel, then likelihood of overflow is reduced, but communication efficiency deteriorates because total packets received cannot exceed resources allotted to a single virtual channel

Engineering Contradiction:
Improvelikelihood of overflowVSAvoidcommunication efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the communication resources by introducing multiple internal virtual channels (e.g., VC0, VC1, VC2) that map to a single link virtual channel. Each internal virtual channel has its own dedicated resources (buffers, pointers, FIFOs), allowing independent packet handling and flow control. This segmentation enables the system to maintain reliability by distributing resources across multiple channels while improving efficiency by allowing parallel processing of packets from different internal channels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a nested virtual channel structure where internal virtual channels are contained within the link virtual channel framework. The link virtual channel contains multiple internal virtual channels, each with its own resource allocation. This nesting allows the system to maintain the external simplicity of link-level flow control while incorporating internal complexity for finer-grained resource management, resolving the contradiction between reliability and efficiency.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Adaptability or versatility

If multiple internal virtual channels are supported by mapping to a single link virtual channel, then flexibility in packet reordering and priority handling is improved, but device complexity increases due to mapping requirements in both transmitting and receiving devices

Engineering Contradiction:
Improveflexibility in packet reorderingVSAvoidmapping support complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces mapping tables as intermediary structures that mediate between link virtual channels and internal virtual channels. These tables (e.g., VC0 maps to {IC0, IC1}, VC1 maps to {IC2}) provide a systematic way to translate between the two virtual channel hierarchies, reducing the complexity of direct mapping requirements. The mapping tables act as intermediaries that simplify the coordination between transmitting and receiving devices.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent makes the virtual channel mapping mechanism universal by implementing the same mapping approach in both transmitting and receiving devices. The mapping tables and resource allocation schemes are designed to work consistently across both ends, allowing the system to leverage the same mechanisms for packet reordering, priority handling, and flow control without requiring device-specific complex coordination.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If separate resources are allocated to various virtual channels, then communication errors and deadlock are avoided, but resource utilization efficiency decreases when multiple internal virtual channels share link-level resources

Engineering Contradiction:
Improvecommunication errors and deadlockVSAvoidresource utilization efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments resources at the internal virtual channel level while maintaining link-level resource sharing. Each internal virtual channel has dedicated buffers and pointers, preventing resource conflicts and deadlock at the internal level. Meanwhile, the link-level flow control mechanism ensures efficient utilization by allowing multiple internal channels to share the same physical link resources in a coordinated manner, avoiding the waste associated with allocating separate physical resources to each virtual channel.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial resource allocation by providing separate resources only where necessary (at the internal virtual channel level for packet buffering and flow control) while allowing resource sharing at the link level. This partial segmentation provides sufficient isolation to prevent deadlock and errors while avoiding the excessive resource allocation that would be required if every virtual channel had dedicated physical resources, thereby improving overall resource utilization efficiency.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8144585B2Data processing device interface and methods thereof
Publication Date: 2012.03.27 ADVANCED MICRO DEVICES INC
  • US8144585B2 patent drawing
  • US8144585B2 patent drawing
  • US8144585B2 patent drawing

AI summary

A method of receiving communications at a data processing device includes receiving a packet from a virtual channel associated with a physical communication link. The packet is associated with a link virtual channel, and is stored in a storage location with the link virtual channel. Multiple internal virtual channels can be associated with the link virtual channel. A pointer to the storage location is enqueued in one of a plurality of FIFOs associated with one of the internal virtual channels. Each FIFO of the plurality of FIFOs stores pointers associated with a different internal virtual channel, allowing receiver arbitration logic to reorder between internal virtual channels based on internal resource availability and current priorities among virtual channels. This reduces the likelihood of communication deadlock and supports multiple classes of service.