Virtual Channel Write Table for Memory Bandwidth
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Solution Overview
Problem
In computer systems, particularly in systems-on-chip (SoCs), memory transaction bottlenecks occur due to the need for successive read or write transactions to wait until prior transactions complete, limiting bandwidth and efficiency in memory access.
Innovation Solution
The implementation of a communication fabric that routes transactions between source circuits and system memory, using a processing circuit to manage write transactions by allocating entries in a write table and maintaining pending requests in a buffer, allowing for concurrent processing and tracking of transactions without waiting for prior completions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If successive read or write transactions wait for prior transactions to complete, then transaction ordering is maintained, but bandwidth and memory access efficiency are limited
Solution Approach 1:
The patent segments the single transaction queue into multiple virtual channels (VC0, VC1, VC2, VC3), allowing independent transactions from different sources to be processed concurrently. Each virtual channel maintains its own queue, enabling out-of-order processing while preserving in-order delivery within each channel, thereby increasing memory bandwidth and reducing wait times.
Solution Approach 2:
The patent introduces a new dimension of parallelism by adding virtual channel identifiers to transactions. Instead of a single-dimensional sequential processing queue, the system now processes transactions across multiple virtual channel dimensions simultaneously, allowing overlapping execution of independent memory operations without compromising ordering guarantees.
2Reliability
If a large pending request buffer is used to track all write transactions, then transaction tracking is comprehensive, but resource consumption and power usage increase
Solution Approach 1:
The patent segments the monolithic pending request buffer into multiple smaller per-VC pending request buffers. Each virtual channel has its own dedicated buffer, allowing the system to track transactions reliably within each channel while using significantly less total memory capacity. This segmentation reduces the overall power consumption associated with maintaining large buffer structures.
Solution Approach 2:
The patent applies local quality by allocating buffer resources specifically to virtual channels that have pending write transactions. Instead of maintaining a uniformly large buffer for all possible transactions, the system dynamically allocates tracking resources to where they are actually needed, reducing unnecessary power consumption from idle buffer capacity while maintaining reliable tracking for active transactions.
3Productivity
If multiple virtual channels share a single physical interface, then bandwidth is improved, but channel management complexity increases
Solution Approach 1:
The patent applies preliminary action by assigning each transaction to a specific virtual channel queue at the time of transaction generation, before the transaction reaches the physical interface. This upfront assignment simplifies subsequent processing at the physical interface, as transactions are already organized by virtual channel and can be dispatched efficiently without complex real-time arbitration or routing decisions.
Data Source
AI summary
An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.