Virtual Chip Yield Prediction for Wafer Defect Mapping
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Solution Overview
Problem
Semiconductor wafers are prone to contamination during processing, leading to defects such as hot spots, which can result in decreased productivity and quality due to defocus issues, and existing methods fail to effectively predict and prevent these defects across the entire wafer and equipment areas.
Innovation Solution
A method and apparatus that utilize wafer-level data to generate virtual chips, map test results, compute defect rates, and calculate a defect index to predict semiconductor yield by identifying and quantifying defects on both the frontside and backside of wafers, as well as in specific equipment areas, enabling early defect detection and process optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wafer-level measurement and defect detection are implemented across the entire wafer surface, then manufacturing precision and defect detection capability are improved, but device complexity and measurement time increase
Solution Approach 1:
The patent segments the wafer measurement process into multiple discrete steps: initial wafer-level mapping to identify defect-prone regions, selective chip-level inspection of affected areas, and virtual chip generation for defect correlation. This segmentation allows comprehensive defect detection without requiring exhaustive measurement of the entire wafer surface, thereby reducing system complexity while maintaining high detection capability.
Solution Approach 2:
The patent performs preliminary wafer-level measurement and defect mapping before proceeding to detailed chip-level inspection. By identifying defect-prone regions in advance through wafer-level scanning, the system can focus subsequent measurement resources on specific areas of interest, reducing overall measurement time and system complexity while maintaining high defect detection capability.
2Measurement precision
If comprehensive wafer-level defect detection is performed, then yield prediction accuracy is improved, but measurement time and productivity are reduced
Solution Approach 1:
The patent divides the measurement process into two stages: a rapid wafer-level screening phase that identifies defect-prone regions, followed by a focused chip-level inspection phase that examines only the identified problem areas. This segmentation enables accurate yield prediction through comprehensive defect analysis while minimizing total measurement time by avoiding exhaustive inspection of defect-free regions.
Solution Approach 2:
The patent performs wafer-level measurement that covers the entire wafer surface to identify defect patterns, but then limits detailed chip-level inspection to only those regions where defects were detected. This partial action approach ensures accurate yield prediction by examining all potential defect sources while avoiding redundant measurement of clean areas, thus reducing overall measurement time.
3Manufacturing precision
If defect detection covers both frontside and backside of wafers, then manufacturing precision is improved, but device complexity and processing time increase
Solution Approach 1:
The patent segments the dual-sided inspection process by first performing wafer-level mapping that identifies defects on both frontside and backside, then using this information to guide selective chip-level inspection. The system processes each side systematically and correlates defects between sides through virtual chip generation, achieving comprehensive defect coverage while managing processing time through structured segmentation of the inspection workflow.
4Measurement precision
If virtual chip generation and coordinate transformation are implemented, then defect rate computation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent introduces virtual chips as an intermediary data structure that bridges wafer-level measurement data and chip-level defect analysis. The virtual chip generation process creates a computational model that automatically handles coordinate transformations and defect mapping between different reference frames. This intermediary approach simplifies the overall system by automating complex data processing tasks rather than requiring manual coordinate transformations, thereby improving defect rate computation accuracy while managing data processing complexity through algorithmic automation.
Data Source
AI summary
A method of predicting a semiconductor yield includes receiving wafer level data generated by measuring a plurality of wafers, generating a plurality of virtual chips corresponding to the plurality of wafers based on the wafer level data, mapping a test result of the plurality of wafers to the plurality of virtual chips, computing a defect rate of the plurality of virtual chips according to defects based on a result of the mapping, and computing a defect index of the equipment based on the defect rate.