Virtual Clock Buffering for IC Timing Closure
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Solution Overview
Problem
During the design process of integrated circuits, clock timing violations often arise after the clock tree synthesis stage, making it difficult to synchronize data path components and leading to bottlenecks in design convergence, as post-CTS optimizers are limited by pre-existing clock path constraints.
Innovation Solution
Emulating clock tree synthesis at an earlier stage in the design process allows for virtual determination of clock delays and setup violations, enabling restructuring of clock gates to optimize the clock network before actual synthesis, thereby minimizing violations and improving design convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock tree synthesis is performed after data path optimization, then data path components can be optimized for performance, but clock timing violations cannot be detected or fixed until after CTS, making it too late to resolve setup violations
Solution Approach 1:
The patent performs preliminary clock tree synthesis before data path optimization to establish initial clock timing constraints. This allows the system to anticipate clock timing issues early in the design process, enabling data path components to be optimized with knowledge of future clock constraints, thus preventing timing violations rather than detecting them too late
Solution Approach 2:
The patent implements iterative feedback loops where clock tree synthesis and data path optimization are performed in alternating passes. After each CTS pass, timing violations are analyzed and fed back to guide the next round of data path optimization, progressively improving clock timing closure while maintaining data path performance
2Reliability
If post-CTS optimizers are used to fix clock gating setup violations, then some violations can be corrected, but the clock path is already committed and further modifications worsen symmetry and timing
Solution Approach 1:
The patent makes the clock path dynamic by allowing iterative modifications through multiple passes of CTS and optimization. Instead of committing to a fixed clock path early, the system repeatedly adjusts clock tree synthesis parameters and buffer placements across multiple iterations, enabling violations to be corrected without permanently fixing the clock path structure
Solution Approach 2:
The patent changes key parameters of the clock path during iterative optimization, including buffer insertion points, clock gate placements, and tree synthesis constraints. By dynamically adjusting these parameters across multiple passes, the system can correct timing violations while maintaining or improving clock path symmetry
3Productivity
If pre-CTS optimizers operate on clock gating setup violations in ideal clock mode, then some optimizations can be performed, but they cannot see actual clock delays and violations
Solution Approach 1:
The patent introduces an intermediary estimated clock delay model that bridges ideal clock mode and propagated clock mode. This intermediary representation provides approximate clock timing information during pre-CTS optimization, allowing optimizers to make informed decisions about clock gating setup violations without having actual measured delays, while still enabling meaningful optimizations before CTS
Data Source
AI summary
Achieving clock timing closure in designing an integrated circuit involves virtually synthesizing a clock network for the integrated circuit design to generate virtual clock buffering in the clock network before a point in the design flow at which the clock network is actually synthesized and committed to a netlist. Timing violations are determined for clock gates generated by the virtual clock buffering. Clock gating transforms are evaluated for the clock gates having the timing violations, based on recalculated clock and data path delays, to incrementally virtually synthesize the clock network. The clock gating transforms that result in the best timing gains are committed to the netlist. The clock network is then actually synthesized for the integrated circuit design, and design changes, due to the actual clock network synthesis, are committed to the netlist.