Virtual Clock Management for TSN Attack Recovery

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Solution Overview

Problem

Time-synchronized networks (TSNs) are vulnerable to cyberattacks that disrupt time synchronization, leading to desynchronization of nodes and impact scheduled traffic, which existing intrusion detection systems (IDSs) can only detect after several samples have been consumed, leaving the system with an unusable clock state.

Innovation Solution

Implementing a virtual clock manager that maintains multiple clock control loops at different rates, allowing immediate recovery from network-based attacks by accessing a clean clock state unaffected by malicious time measurements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional intrusion detection systems are used to detect attacks on TSN clocks, then attack detection capability is provided, but the detection occurs after several samples have been consumed leaving the clock state unusable

Engineering Contradiction:
Improveattack detection capabilityVSAvoidtime recovery delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent maintains multiple virtual clocks in advance (primary, secondary, tertiary) that are continuously synchronized at different rates. When an attack is detected, the system immediately switches to a pre-prepared clean clock state rather than recovering from a compromised single clock, eliminating the time loss associated with detection and recovery.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system prepares multiple backup virtual clocks beforehand that can serve as cushioning against attacks. These pre-synchronized clocks act as a buffer, ensuring that when an attack occurs, there is already a clean clock state available to maintain TSN operation without interruption or time loss.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Speed

If multiple virtual clocks are maintained at different synchronization rates, then faster recovery from attacks is enabled, but device complexity increases

Engineering Contradiction:
Improvetime recovery speedVSAvoidclock management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the single clock function into multiple virtual clocks (primary, secondary, tertiary), each operating at different synchronization rates. This segmentation allows the system to isolate attacked clocks from clean clocks, enabling fast recovery by switching between segmented clock instances rather than recovering a single compromised clock.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The virtual clock manager acts as an intermediary that manages multiple virtual clocks and handles the switching logic between them. This intermediary component abstracts the complexity of managing multiple clocks at different rates, providing a unified interface while enabling fast recovery through intelligent clock selection and switching.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If a single hardware clock is used for TSN synchronization, then device complexity is minimized, but the system becomes vulnerable to desynchronization attacks

Engineering Contradiction:
Improveclock structure simplicityVSAvoidvulnerability to timing attacks
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent creates multiple virtual clock copies from a single hardware clock source. These virtual clocks are software-based instances that replicate the clock function but operate independently at different synchronization rates. This copying approach maintains hardware simplicity while providing redundancy against attacks, as compromised virtual clock copies can be discarded and replaced without affecting the hardware or other virtual clocks.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20250379874A1Techniques to manage virtual clocks for a time sensitive network
Publication Date: 2025.12.11 INTEL CORP
  • US20250379874A1 patent drawing
  • US20250379874A1 patent drawing
  • US20250379874A1 patent drawing

AI summary

Techniques include a method, apparatus, system and computer-readable medium to enhance security for time-synchronized networking. A method includes decoding a reference message comprising time information to synchronize a hardware clock of a time sensitive network (TSN) node with a network time for a TSN, the reference message associated with a reference synchronization interval, selecting a virtual clock from a set of virtual clocks for the TSN node, the virtual clock associated with a first synchronization interval that is different from the reference synchronization interval, and adjusting a time for the virtual clock based on the time information from the reference message to synchronize the virtual clock with the network time for the TSN. Other embodiments are described and claimed.