Virtually Clustered Processor Cores and Cache Slices
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Solution Overview
Problem
In multi-core processors, the increased number of cores leads to longer cache hit and miss latencies due to the physical distribution of shared caches, resulting in higher memory access times and reduced effective memory bandwidth.
Innovation Solution
The processor logically or virtually partitions cores and cache slices into clusters, allowing initial access to only nearby cache slices within a virtual cluster, reducing access distances and addressing entropy at memory controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of cores is increased to improve execution throughput, then multiple threads can be performed concurrently, but the average distance between cores and cache slices increases leading to longer cache access latencies
Solution Approach 1:
The shared cache is segmented into multiple cache slices that are physically distributed across the integrated circuit, with each cache slice co-located with or near specific cores. This segmentation allows cores to access nearby cache slices more quickly while maintaining overall cache capacity.
Solution Approach 2:
Different cache slices have different access characteristics based on their physical location relative to cores. Cores have preferential or faster access to nearby cache slices, creating local quality variations in access speed that optimize for both multi-core throughput and individual access latency.
2Productivity
If the number of cores is increased to improve execution throughput, then more concurrent workloads can be processed, but memory address entropy at memory controllers increases resulting in lower effective memory bandwidth
Solution Approach 1:
Memory controllers are segmented and associated with specific virtual clusters or cache slices, distributing the memory access load across multiple controllers. This reduces the address entropy each controller must handle and increases effective memory bandwidth.
3Quantity of substance
If cache slices are physically distributed across the integrated circuit to support multiple cores, then cache capacity is increased, but the distance between cores and cache slices increases leading to longer access times
Solution Approach 1:
A hierarchical cache structure is implemented where smaller, faster cache slices are nested within or near each core, providing quick access for frequently used data. Larger, distributed cache slices provide additional capacity for less frequently accessed data, creating a nested arrangement that balances speed and capacity.
Data Source
AI summary
A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.