Virtually Concatenated Payload Read Address Determination

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Solution Overview

Problem

In SONET/SDH data transfer architectures, determining the read address for multiple groups of virtually concatenated payloads is inefficient due to varying write and read positions, leading to challenges in processing data quickly and synchronously across the network.

Innovation Solution

The design periodically updates the minimum write address and computes the read address using a dual-memory arrangement, where one memory is kept constant for generating read addresses while the other is updated, allowing for efficient determination of the read address across multiple groups.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If data bytes are read from different members at the same position simultaneously, then synchronization is improved, but determining the read address becomes complex due to varying write and read positions

Engineering Contradiction:
ImprovesynchronizationVSAvoidread address determination
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent segments the determination of read address into two distinct parts: first determining the minimum write address across all members, then using this minimum write address to calculate the read address. This segmentation simplifies the overall complexity by breaking down the complex simultaneous determination into sequential, manageable steps.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary determination of the minimum write address before calculating the final read address. By pre-computing the minimum write address from all members' write addresses, the system prepares essential information in advance that simplifies the subsequent read address calculation, ensuring synchronized reading without complex real-time computations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the destination node reads data bytes at a particular position only when all members have received data bytes at that position, then data integrity is improved, but processing speed decreases

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements a feedback mechanism where the system continuously monitors the write addresses of all members and dynamically adjusts the read address based on the minimum write address observed. This feedback loop ensures that the system maintains data integrity by only reading when all members have written, while the automated nature of the feedback mechanism prevents significant processing delays.

Inventive Principle:
Principle #23Feedback

3Quantity of substance

If multiple groups of virtually concatenated payloads are processed, then network capacity is improved, but determining read address quickly and efficiently becomes more difficult

Engineering Contradiction:
Improvenetwork capacityVSAvoidread address determination
Core Design Contradiction:
Quantity of substanceVSDifficulty of detecting and measuring

Solution Approach 1:

The patent applies partial action by focusing only on the minimum write address among all members rather than tracking every individual write address. This partial determination approach maintains network capacity for multiple groups while simplifying the measurement and detection requirements to only the essential minimum value needed for synchronized reading.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS7508830B1Method and apparatus differential delay compensation processing of virtually concatenated data
Publication Date: 2009.03.24 INTEL CORP
  • US7508830B1 patent drawing
  • US7508830B1 patent drawing
  • US7508830B1 patent drawing

AI summary

A method and apparatus for determining a read address for received data in a communications network employing virtually concatenated payloads is provided. The method and apparatus comprise determining a minimum write address using a plurality of memory elements and using the minimum write address in connection with received read addresses to determine group read addresses.