Virtual Connectivity Change for IC Failure Analysis
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Solution Overview
Problem
Current focused ion beam (FIB) operations for integrated circuit failure analysis are time-consuming and costly, heavily dependent on user skill, and lack assurance of electrical connectivity before physical modifications, which can lead to costly mistakes and damage to circuits.
Innovation Solution
A method and computer program product for performing virtual connectivity changes between nets in an integrated circuit, allowing simulation of FIB cuts and deposits within a virtual environment to verify electrical connectivity before physical operations, reducing guesswork and potential damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FIB operations are performed to repair failed portions of IC chip, then electrical connectivity can be restored, but the process is time-consuming and costly
Solution Approach 1:
The patent performs preliminary actions by simulating FIB operations in a virtual environment before executing them on the actual IC chip. The system uses EDA tools to create a virtual model of the chip, allows users to plan and simulate connectivity changes, and verifies the effectiveness of proposed repairs virtually. This preliminary virtual execution prevents unnecessary physical FIB operations, thereby reducing time loss while ensuring reliable electrical connectivity restoration.
2Measurement precision
If FIB operations are performed to locate failure, then failure location can be identified, but it is often a guess and heavily dependent on user skill
Solution Approach 1:
The patent introduces an intermediary system consisting of EDA tools and virtual simulation environment that mediates between the user and the actual FIB operation. The system provides automated guidance through virtual models, allowing users to visualize and plan precise failure location identification without requiring extensive expertise. The intermediary virtual environment translates complex chip structures into intuitive graphical representations, reducing user skill dependency while improving measurement precision for failure location identification.
3Reliability
If physical FIB operations are performed on IC, then connectivity can be verified, but there is risk of damaging the circuit if operation is incorrect
Solution Approach 1:
The patent applies preliminary anti-action by using virtual simulation to counteract potential harmful effects before they occur in physical operations. The system allows users to test and verify connectivity changes in a risk-free virtual environment, identify potential errors, and correct them before executing actual FIB operations. This preliminary counter-measurement prevents incorrect physical operations that could damage the circuit, while still ensuring reliable connectivity verification through the virtual model.
4Reliability
If multiple layers are involved in net connectivity, then complex electrical paths exist, but verifying connectivity becomes more difficult
Solution Approach 1:
The patent transitions from two-dimensional planar views to three-dimensional virtual models to better visualize and verify connectivity across multiple layers. The EDA tools generate 3D representations of the chip structure, allowing users to navigate and inspect electrical paths through multiple layers from different angles and perspectives. This dimensional enhancement makes it easier to detect and measure connectivity relationships in complex multi-layer networks while maintaining reliable electrical connectivity verification.
Data Source
AI summary
A method of performing virtual connectivity change between first and second nets associated with an integrated circuit is presented. The method includes generating a first top view and a first perspective views of a layout of the integrated circuit when a computer is invoked to perform the virtual connectivity change. The method further includes defining layers associated with the first and second nets, and defining a boundary of the virtual connectivity change. The method further includes performing the virtual connectivity change between the first and second nets within the boundary, and generating a second top view and a second perspective view of the layout of the integrated circuit after the virtual connectivity change.