Virtual Core Register Reference Instruction for Low-Overhead Debugging
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Solution Overview
Problem
Existing methods for verifying program operations on virtual cores are hindered by high overhead, interference with the program's operation, and limited versatility, especially when the operating system is stalled or during real-time tracing, due to the need for dedicated hardware and complex synchronization processes.
Innovation Solution
A central processing unit (CPU) and information processing apparatus that enable direct reference to a current register value of an arbitrary virtual core without influencing its execution context, using a reference instruction that can be executed on another virtual core on the same physical core, with permission switching capabilities to minimize overhead and allow for analysis, debugging, and parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated hardware (JTAG, ICE) is used to acquire register information, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the register information acquisition function from dedicated external hardware (JTAG, ICE) and implements it within the CPU itself through virtual core mechanisms. This allows register information to be read without external devices, reducing hardware complexity while maintaining measurement precision.
Solution Approach 2:
The patent makes the CPU serve multiple functions: it既可以 execute normal programs on virtual cores,又可以 acquire register information for verification. The same CPU hardware that runs applications also performs verification functions, eliminating the need for separate dedicated verification hardware.
2Reliability
If traditional verification methods (debugger, memory dump) are used, then verification capability is improved, but productivity decreases due to program interruption
Solution Approach 1:
The patent enables continuous program execution on virtual cores while simultaneously performing verification. The verified virtual core continues executing without interruption, and verification is performed through register reading mechanisms that do not halt the program flow, maintaining both reliability and productivity.
Solution Approach 2:
The patent introduces virtual cores as intermediaries between the physical core and the verification process. Register information is acquired through the virtual core interface without directly interrupting the program execution on the virtual core, allowing verification to proceed without stopping the program.
3Loss of time
If register information is copied to different area for reading, then loss of time is reduced, but loss of information increases due to synchronization requirements
Solution Approach 1:
The patent uses virtual cores that maintain register state copies synchronized with the physical core. These virtual register copies can be read without interrupting the physical core execution, reducing reading time while maintaining information accuracy through the virtualization layer's synchronization mechanisms.
Data Source
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AI summary
To provide a new operation verification method for an information processing flow, a central processing unit capable of building a plurality of virtual cores on a physical core includes: an element or part for executing, on an own virtual core, or causing another virtual core on the same physical core to execute, a reference instruction of directly referring to a current register value used by an arbitrary virtual core from the another virtual core without influence on an execution context of the arbitrary virtual core; and an element or part for switching a permission or authorization for executing the reference instruction of referring to the register value among the plurality of virtual cores.