Virtual Cores Partition Instruction Sequences for Processor Efficiency
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Solution Overview
Problem
Current processor architectures face inefficiencies in handling multiple threads due to the overhead of context switching and the complexity of duplicating architecture state elements for each thread, especially in fine-grain parallelism scenarios, where existing thread-aware hardware does not adequately support non-threaded software code and incurs significant software overhead.
Innovation Solution
A processor design that utilizes a global front-end scheduler to partition instruction sequences into code blocks and generate inheritance vectors, allowing virtual cores to execute instructions across partitionable engines with a common register file and memory subsystem, enabling efficient execution of multiple threads through fragmented address spaces and multiport bank storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If hardware duplicates all architecture state elements for each supported thread, then context switch overhead is eliminated, but area, power consumption and hardware complexity increase significantly
Solution Approach 1:
The processor architecture segments the register file into multiple banks (e.g., Bank 0, Bank 1, Bank 2, Bank 3) that can be independently accessed by different threads. Each thread is assigned to specific banks, allowing parallel access without full duplication of all register state. This segmentation reduces the complexity of maintaining complete architecture state for each thread while enabling efficient context switching through bank-specific operations.
Solution Approach 2:
The patent introduces a new dimension of organization by implementing thread-specific register banks within a unified register file structure. Instead of duplicating entire register files for each thread (3D approach), the system uses a 2D organization where threads are mapped to specific banks within a shared register file, reducing space complexity while maintaining thread independence through bank indexing.
2Productivity
If hardware supports multiple context states for limited threads, then context switching is reduced, but the area and power consumption increase due to duplicating architecture state elements
Solution Approach 1:
Multiple thread contexts are merged into a single unified register file structure with banked organization. Instead of maintaining separate complete register files for each thread (which would increase power consumption), the system combines thread states into shared banks that can be selectively activated. The bank-specific load/store operations allow efficient context switching without maintaining all thread states simultaneously in full duplication, reducing overall power consumption while supporting multiple threads.
3Productivity
If fine-grain parallelism requires a large number of threads, then processing capability increases, but software overhead for initiating and synchronizing threads increases heavily
Solution Approach 1:
The processor implements self-service mechanisms for thread management through automatic bank assignment and context identification. When a thread is initiated, the hardware automatically assigns it to available banks and manages the context state without requiring extensive software intervention for synchronization and thread initiation. The bank-specific load/store operations provide automatic context management, reducing the software overhead for fine-grain parallelism while maintaining high thread count capability.
Data Source
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AI summary
A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage.