Virtual CPU Bus Error Recovery via Segmented Interrupts

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Solution Overview

Problem

In computer systems with multiple virtual machines, an IO error in one virtual machine can propagate to other virtual machines sharing the same hardware, leading to abnormal terminations of operating systems that do not recognize the faulty bus, causing unintended failures.

Innovation Solution

A multithreaded processor with an interrupt controller that notifies bus errors and reinitializes the affected bus by prioritizing the first virtual CPU to manage other virtual CPUs, ensuring only the management OS operates to reinitialize the bus and prevent failure propagation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple operating systems run on shared hardware through virtual machines, then hardware utilization efficiency is improved, but failure propagation between operating systems occurs when IO errors happen

Engineering Contradiction:
Improvehardware utilization efficiencyVSAvoidfailure propagation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the system into virtual machine environments with isolated operating systems, where each OS runs in its own virtualized space. When an IO error occurs in one VM, the error is contained within that specific virtual environment and cannot propagate to other VMs or their operating systems, thus maintaining system reliability while allowing multiple OSes to share hardware resources.

Inventive Principle:
Principle #1Segmentation

2Reliability

If an IO error occurs in one virtual machine, then the affected virtual machine can be stopped to prevent error expansion, but other virtual machines using the same bus may abnormally terminate due to unrecognized bus faults

Engineering Contradiction:
Improveerror containmentVSAvoidbus error propagation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a bus bridge as an intermediary component between the IO devices and the virtual machines. The bus bridge detects IO errors and generates interrupt signals to notify the affected virtual machine. This intermediary mechanism allows the system to identify and contain errors within specific VMs while preventing unintended propagation to other VMs that share the same bus, thus resolving the contradiction between error containment and harmful factor generation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If the same hardware runs multiple operating systems, then resource sharing and versatility are improved, but failure isolation becomes difficult when bus errors occur

Engineering Contradiction:
Improveresource sharingVSAvoidfailure isolation
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the hardware resources into virtualized components allocated to different virtual machines. Each virtual machine has its own virtual bus interface through the bus bridge, creating logical isolation even though physical hardware is shared. This segmentation allows multiple operating systems to share hardware resources effectively while maintaining failure isolation, as errors in one VM cannot affect other VMs due to the virtualization boundary.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bus bridge acts as an intermediary that manages communication between multiple virtual machines and shared IO devices. It implements error detection and notification mechanisms that ensure failures are isolated to specific VMs. The bus bridge translates physical bus errors into targeted interrupt signals for the affected VM only, preventing failure propagation while maintaining resource sharing capabilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10379931B2Computer system
Publication Date: 2019.08.13 RENESAS ELECTRONICS CORP
  • US10379931B2 patent drawing
  • US10379931B2 patent drawing
  • US10379931B2 patent drawing

AI summary

A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.