Virtual CPU Task Parallelization for Host Hardware Emulation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional virtualization techniques struggle to achieve performance parity or acceleration with native processor execution, especially as the performance gap between target and host hardware platforms narrows, making it difficult to emulate complex systems effectively in test facilities and trainers.

Innovation Solution

The method involves identifying tasks in a virtualization layer and parallelizing their execution across additional physical CPUs of the host hardware platform, hidden from the operating system, allowing for execution before scheduled times and utilizing method stubs or moving to next-scheduled tasks, thereby achieving performance improvements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional virtualization techniques are used to emulate a target hardware platform, then the virtualization platform can provide control and visibility, but the execution performance is slower than native processor execution

Engineering Contradiction:
Improvefidelity of system representationVSAvoidexecution performance
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the execution of computer program tasks across multiple virtual processors (VCPUs) that map to physical cores. By dividing the workload into parallel-executable task segments and distributing them across available CPU resources, the system achieves both high-fidelity emulation and improved execution performance through parallel processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to task execution by allowing tasks to be executed before their scheduled times when CPU resources are available. This out-of-order execution, managed through a scheduling system that tracks task dependencies and CPU availability, enables performance acceleration while maintaining the logical execution sequence expected by the emulated system.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If the performance gap between target and host hardware platforms narrows, then the host hardware becomes faster, but achieving performance parity or acceleration becomes more difficult

Engineering Contradiction:
Improvehost hardware performanceVSAvoidemulation performance
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent performs preliminary analysis of the computer program to identify parallelizable tasks and their dependencies before execution. The scheduling system pre-processes the task graph to determine which tasks can be executed in parallel and on which VCPUs, enabling the system to fully utilize available CPU resources even when the host hardware performance is comparable to the target platform.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically adjusts execution parameters including the number of active VCPUs, task allocation strategies, and scheduling intervals based on the performance characteristics of the host hardware. When the performance gap narrows, the system can activate more VCPUs and use more aggressive parallelization strategies to maintain or achieve performance acceleration.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If tasks are executed on additional virtual processors before scheduled times, then performance improves, but the operating system must be modified or additional virtual processors must be hidden

Engineering Contradiction:
Improvetask execution speedVSAvoidvirtualization layer complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a scheduling layer as an intermediary between the emulated operating system and the physical CPU resources. This scheduling system translates the OS's task scheduling requests into parallel execution commands that utilize multiple VCPUs, while presenting a unified, unchanged interface to the operating system. The complexity is contained within the virtualization layer rather than requiring OS modifications.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3007065B1Parallelization in virtual machine operation
Publication Date: 2020.03.11 THE BOEING CO
  • EP3007065B1 patent drawingFigure 1A~1C
  • EP3007065B1 patent drawingFigure 2
  • EP3007065B1 patent drawingFigure 3~5

AI summary

According to a method of providing virtualization services, computer program(s) executable as a plurality of tasks may be identified, as may task(s) from the plurality of tasks. The computer program(s) (122) may be executed by virtual central processing unit(s) (CPUs) (118a) in a virtual machine (114) executed on a host hardware platform and defined to provide a virtualization platform (116) for virtualization of a target hardware platform. This may include the plurality of tasks other than the (identified) task(s) being executed by the virtual CPU(s) (118a) in the virtual machine (116) executed on CPU(s) (104a) of the host hardware platform, and at least partially in parallel with these tasks, executing the task(s) on additional CPU(s) (104b) of the host hardware platform. The target hardware platform may include CPU(s) (104a) for execution the plurality of tasks no greater in number than the CPU(s) of the host hardware platform on which the plurality of tasks other than the task(s) are executed.