Virtual Defect Test Pattern Generation for IC Fault Detection

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Solution Overview

Problem

Integrated circuits often suffer from defects such as parasitic resistance, capacitance, and disconnections, which can lead to incorrect logic computations, and existing test patterns may not detect unmodeled defects efficiently, requiring computationally exhaustive simulations.

Innovation Solution

A method is introduced to generate test patterns based on virtual defects, which are assigned to input conditions irrespective of physical characteristics, allowing for the detection of unmodeled defects without the need for costly simulations, and additional test patterns are generated to supplement existing ones by simulating fault detection and reducing tables of logic behavioral models.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If computationally exhaustive simulations are performed to detect all possible defects, then defect detection completeness is improved, but computational cost and time consumption increase

Engineering Contradiction:
Improvedefect detection completenessVSAvoidcomputational time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the defect detection process by dividing all possible defects into two categories: modeled defects (with known physical characteristics) and unmodeled defects (without specific physical characteristics). This segmentation allows the testing system to use different approaches for each category, avoiding computationally exhaustive simulations for all defects while ensuring comprehensive coverage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary action by generating test patterns specifically designed to detect unmodeled defects before actual circuit testing. By using virtual defects to pre-generate these test patterns, the system identifies potential failure modes in advance, allowing for efficient targeted testing rather than exhaustive simulation during production testing.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If test patterns are generated based on physical characteristics of defects, then detection accuracy for modeled defects is improved, but ability to detect unmodeled defects deteriorates

Engineering Contradiction:
Improvedefect detection accuracyVSAvoiddefect type coverage
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent applies universality by creating a dual-mode test pattern generation system that can handle both modeled defects (with physical characteristics) and unmodeled defects (without specific physical characteristics). The system uses virtual defects as a universal approach that can represent any defect type, making the testing framework adaptable to various defect scenarios without requiring specific physical models for each defect type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces virtual defects as an intermediary concept between physical defect characteristics and test pattern generation. Virtual defects serve as abstract representations that mediate between the specific physical characteristics of real defects and the general test pattern creation process, enabling the system to generate effective test patterns for both modeled and unmodeled defects through a unified approach.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20220237353A1Fault detection of circuit based on virtual defects
Publication Date: 2022.07.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20220237353A1 patent drawing
  • US20220237353A1 patent drawing
  • US20220237353A1 patent drawing

AI summary

Disclosed herein are related to a method, a device, and a non-transitory computer readable medium for testing a circuit model in an integrated circuit. In one aspect, to each of a plurality of sets of input conditions of a circuit model, a corresponding virtual defect is assigned. The virtual defect may be generated irrespective of a physical characteristic of an integrated circuit formed according to the circuit model. Each virtual defect may be associated with a corresponding set of input conditions. In one aspect, a table of the circuit model including a plurality of logic behavioral models of the circuit model is generated. Each of the plurality of logic behavioral models may include a corresponding set of the plurality of sets of input conditions, a corresponding output result, and the corresponding virtual defect. Based at least in part on the table of the circuit model, a test pattern for the circuit model can be generated.