Static Timing Analysis Using Virtual Delay Arcs
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Solution Overview
Problem
In electronic circuit design, static timing analysis is challenging due to the complexity of mapping logic components to hardware resources, particularly in field programmable gate arrays (FPGAs), where multiple logic components may map to a single hardware resource, making it difficult to reconcile timing issues with the design components and connections.
Innovation Solution
A method that maps logic components to physical components of an integrated circuit, determining logic delay arcs from physical delay arcs, and performing static timing analysis to provide a description of the timing characteristics, allowing designers to identify and address timing issues at the logical level rather than the physical level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple logic components are mapped to a single hardware resource to improve hardware utilization, then device complexity is reduced and resource efficiency is improved, but it becomes difficult to reconcile timing analysis results with design components
Solution Approach 1:
The patent creates a virtual mapping that copies the physical hardware structure into the logical design space. By generating virtual delay arcs that mirror the actual physical delay arcs, the system allows timing analysis to be performed at the logical level while maintaining accuracy. This copying approach enables designers to work with logical components without being constrained by physical mapping complexities.
Solution Approach 2:
The patent introduces a virtual mapping layer as an intermediary between the logical design and physical implementation. This virtual mapping includes virtual delay arcs that act as mediators, translating physical timing constraints into logical design terms. The intermediary layer allows timing analysis to bridge the gap between logical components and physical hardware resources without requiring direct correspondence.
2Measurement precision
If static timing analysis is performed using physical delay arcs to improve timing accuracy, then measurement precision is improved, but it becomes difficult to correlate timing issues with logical design components
Solution Approach 1:
The patent creates virtual delay arcs that copy the structure and timing characteristics of physical delay arcs into the logical design space. This copying allows timing analysis to be performed with physical-level accuracy while presenting results in terms of logical components. The virtual arcs maintain the timing precision of physical measurements while being accessible through the logical design interface.
Solution Approach 2:
Instead of mapping timing analysis results from the physical level back to the logical level (the conventional difficult approach), the patent inverts the process by bringing physical delay arc information forward into the logical design space. This inversion allows designers to perform timing analysis directly on logical components with physical-level accuracy, eliminating the need to translate results back and forth between abstraction levels.
3Measurement precision
If logic delay arcs are determined from physical delay arcs to maintain timing accuracy, then measurement precision is improved, but the mapping complexity increases
Solution Approach 1:
The patent determines logic delay arcs by copying information from physical delay arcs rather than creating entirely new timing models. The virtual delay arcs in the logical mapping copy the timing characteristics, structure, and relationships of the physical delay arcs. This copying approach maintains measurement precision while avoiding the complexity of developing separate timing models for each logical component.
Data Source
AI summary
Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.