Virtual Fabrication Analytics for Semiconductor Specification Limits
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Solution Overview
Problem
The complexity of advanced semiconductor fabrication processes, particularly at technology nodes like FinFET and High-K/Metal-Gate, leads to inefficient and costly trial-and-error experimental methodologies, where conventional CAD and TCAD tools fail to model the entire integrated process flow effectively, resulting in structural failures and prolonged time-to-market.
Innovation Solution
A virtual fabrication environment with an analytics module that performs Design of Experiments (DOE) simulations, builds multiple 3D models, and determines specification limits using non-normally distributed virtual metrology data, enabling the estimation of extremes and sigma equivalent cutoffs, thus allowing for better understanding and setting of correct specification limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If trial-and-error experimental methodology is used to develop semiconductor fabrication processes, then process development can be performed with conventional tools, but the cost and duration of development increase significantly
Solution Approach 1:
The patent applies preliminary action by performing virtual fabrication simulations and DOE studies before actual wafer fabrication. The system pre-determines process parameters, specification limits, and process windows through computational modeling, allowing engineers to optimize processes in silico before committing to expensive and time-consuming physical fabrication trials.
Solution Approach 2:
The patent creates a virtual copy of the fabrication process through a digital twin environment that replicates physical fabrication behavior. This virtual fabrication system uses computational models to mimic material deposition, etching, and other fabrication processes, enabling researchers to study and optimize processes without consuming physical materials or equipment time.
2Ease of manufacture
If trial-and-error experimental methodology is used to develop semiconductor fabrication processes, then process development can be performed with conventional tools, but the cost of experimental runs increases significantly
Solution Approach 1:
The patent creates a virtual copy of the fabrication process through a digital twin environment that replicates physical fabrication behavior. This virtual fabrication system uses computational models to mimic material deposition, etching, and other fabrication processes, enabling researchers to study and optimize processes without consuming physical materials or equipment time.
Solution Approach 2:
The patent replaces physical mechanical fabrication systems with computational modeling systems. Instead of using actual fabrication equipment to run experimental trials, the system uses software-based virtual fabrication that substitutes physical processes with mathematical models, eliminating material costs and equipment usage costs.
3Manufacturing precision
If TCAD tools are used to model semiconductor device structures, then physics-based simulations can be performed, but the simulations are restricted to very small regions and cannot cover the entire integrated process flow
Solution Approach 1:
The patent applies segmentation by dividing the fabrication process into discrete process modules that can be independently modeled and simulated. Each process step (deposition, etching, annealing, etc.) is represented as a separate computational module that can be executed and analyzed independently, then integrated to form the complete process flow.
Solution Approach 2:
The patent transitions from 3D spatial modeling limited to small regions to a process-flow dimension that encompasses the entire fabrication sequence. By organizing simulations around process steps rather than spatial regions, the system can model the complete integrated process flow from wafer input to final device output, covering all process interactions across the entire fabrication timeline.
4Ease of operation
If conventional CAD tools are used to model semiconductor device structures, then design work can be performed, but the tools do not automatically mimic the material addition, removal, and modification processes that occur in an actual fab
Solution Approach 1:
The patent replaces physical mechanical fabrication systems with computational modeling systems. Instead of using actual fabrication equipment to run experimental trials, the system uses software-based virtual fabrication that substitutes physical processes with mathematical models, eliminating material costs and equipment usage costs.
Solution Approach 2:
The patent creates a multi-functional platform that combines design, simulation, and process modeling capabilities in a single integrated system. The virtual fabrication environment can perform both traditional CAD functions and advanced process simulation, making it universally applicable to both design and manufacturing engineering tasks.
Data Source
AI summary
A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for determining specification limits using a fitting algorithm for non-normally distributed virtual metrology data is discussed.