Virtual FPGA Fabric Compilation from High-Level Language Kernels
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Solution Overview
Problem
Current programmable logic devices require extensive knowledge of hardware description languages like VHDL or Verilog for configuration, which can be a barrier for users not proficient in these languages, and the compilation process is time-consuming, especially for complex designs.
Innovation Solution
The use of high-level programming languages such as OpenCL, where kernels are compiled into hardware circuits using a Low-Level Virtual Machine compiler, allowing for the creation of virtual fabrics that can be precompiled and reused, reducing compilation time through a library of preconfigured virtual fabrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If hardware description languages (VHDL/Verilog) are used for configuration, then configuration capability is achieved, but user accessibility deteriorates due to language complexity
Solution Approach 1:
The patent introduces a high-level programming language interface that acts as an intermediary between the user and the hardware description language. Users write code in a familiar high-level language, which is then automatically translated into VHDL or Verilog by a compiler or synthesis tool. This mediator layer shields users from the complexity of hardware description languages while still enabling full configuration capability.
Solution Approach 2:
The patent replaces the manual, mechanical process of writing hardware description language code with an automated compilation process. Instead of users directly crafting VHDL or Verilog code, the system automatically generates the hardware description from high-level language source code through compilation, substituting the manual coding mechanism with an automated translation mechanism.
2Adaptability or versatility
If complex logic designs are implemented, then functionality is improved, but compilation time increases excessively
Solution Approach 1:
The patent implements a two-stage compilation process where common logic patterns and hardware modules are pre-compiled and stored as reusable templates or IP cores. When configuring a device, the system first performs a high-level placement and routing using these pre-compiled modules, then only compiles the custom logic that connects them. This preliminary preparation of common components significantly reduces the compilation time for complex designs.
Solution Approach 2:
The patent divides the compilation process into separate stages: a fast high-level placement and routing stage that uses pre-compiled module templates, and a subsequent detailed compilation stage for custom logic. This segmentation allows the majority of the design (using standard modules) to be processed quickly, while only the unique portions require full compilation attention.
Data Source
AI summary
A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.