Virtual GPIO Consolidation Over Serial Bus

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Solution Overview

Problem

Mobile communication devices face challenges in achieving low-latency serial communication between peripherals and application processors due to the latency associated with serial data links, which hinders the conversion of physical command and control signals to virtual signals, especially in real-time embedded systems.

Innovation Solution

A virtual GPIO finite state machine (VGI FSM) is introduced to consolidate GPIO state information from multiple sources and distribute it over a data communication bus, allowing GPIO signals to be carried as virtual signals, reducing the need for physical interconnects and minimizing latency by using protocols like SPMI and RFFE.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If physical interconnects are used for command and control signals, then signal transmission is reliable, but the number of GPIO pins consumed increases

Engineering Contradiction:

ImproveGPIO pin availabilityVSAvoidphysical interconnect structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates virtual copies of physical GPIO signals by encoding their state information into data packets transmitted over existing serial communication links. Instead of requiring physical interconnects for each GPIO signal, the system transmits replicated state information digitally, allowing the same GPIO state to be accessed by multiple devices without additional physical pins.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent makes existing serial communication links multi-functional by enabling them to carry both their original data communication function and GPIO command/control signal function simultaneously. The serial bus is used universally for both purposes, eliminating the need for dedicated GPIO pins and reducing overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If serial data links are used to carry GPIO signals, then the number of physical pins is reduced, but transmission latency increases

Engineering Contradiction:

Improvephysical pin reductionVSAvoidsignal transmission latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by pre-configuring the serial communication links to recognize and prioritize GPIO-related data packets. The system prepares the communication infrastructure in advance to handle GPIO signal transmissions efficiently, reducing the time required when actual GPIO state changes need to be communicated.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameter of data packet structure by implementing specific packet formats with dedicated fields for GPIO state information. This allows receiving devices to quickly identify and process GPIO-related packets without parsing entire data streams, effectively reducing transmission latency through optimized data representation.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If virtual GPIO signals are implemented over existing serial links, then manufacturing cost is reduced, but protocol compatibility challenges arise

Engineering Contradiction:

Improvemanufacturing costVSAvoidprotocol compatibility

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent segments the communication protocol into distinct layers: the physical serial communication layer remains unchanged to maintain compatibility with existing devices, while a higher-layer virtual GPIO protocol is superimposed on top. This segmentation allows the underlying serial link to continue operating according to its original protocol while enabling new GPIO functionality through standardized packet formats.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary virtualization layer that translates between physical GPIO states and virtual signal representations transmitted over serial links. This intermediary layer handles protocol conversion and state mapping, allowing different serial protocols (I2C, SPI, UART) to all support virtual GPIO functionality without requiring changes to the underlying physical communication standards.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10467154B2Multi-port multi-sideband-GPIO consolidation technique over a multi-drop serial bus

Publication Date: 2019.11.05 QUALCOMM INC

AI summary

Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.