Virtual GPIO Port Multiplexer for Microcontroller Pin Mapping
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Solution Overview
Problem
Current microcontrollers with low pin counts face limitations in simultaneously driving or sampling multiple GPIO pins due to pin multiplexing, requiring multiple instruction cycles and lacking coherent access across ports, especially when peripherals are densely allocated.
Innovation Solution
A microcontroller system with a virtual GPIO port that maps unrelated pins to a single software port using a multiplexer and additional registers, allowing programmable assignment of pins and switching between different configurations with minimal additional logic, treating GPIO as a re-mappable peripheral.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple peripherals are multiplexed onto each pin to reduce pin count, then device integration is improved, but the ability to access multiple GPIO pins coherently with a single instruction is degraded
Solution Approach 1:
The patent introduces an intermediary mechanism (virtual port mapping logic) that sits between the physical pins/peripherals and the software access interface. This intermediary allows multiple scattered GPIO pins to be virtually grouped into a single port, enabling coherent access through a single register operation while preserving the underlying multiplexed peripheral architecture.
Solution Approach 2:
The patent creates a universal virtual port interface that can represent any combination of physical GPIO pins regardless of their actual port assignments. This universal interface allows the same software mechanism to access scattered pins across multiple physical ports, providing multi-functional access capability through a unified register interface.
2Adaptability or versatility
If GPIO pins are scattered across multiple physical ports, then pin allocation flexibility is improved, but the ability to drive or sample multiple pins simultaneously is degraded
Solution Approach 1:
The patent creates a virtual copy or abstraction of the physical port structure. Instead of requiring software to manually coordinate multiple physical ports, the system creates a virtual port that copies the functionality of multiple scattered pins into a unified interface, allowing simultaneous drive or sample operations through a single atomic register access.
Solution Approach 2:
The patent merges scattered GPIO pins from multiple physical ports into a single virtual port entity. This merging allows the pins to be accessed and operated upon simultaneously through unified register operations, while the underlying physical pin assignments remain flexible and can be reconfigured.
3Reliability
If dedicated pin functions are assigned to specific peripherals, then peripheral functionality is improved, but the availability of GPIO functions on those pins is degraded
Solution Approach 1:
The patent implements a dynamic pin assignment system where the functionality of pins can be reconfigured through software. The virtual port mechanism allows GPIO functions to be dynamically assigned to pins that may also serve peripheral functions, enabling flexible adaptation of pin roles without hardware changes or extensive re-programming.
Solution Approach 2:
The patent segments the pin functionality into separate controllable units through the virtual port interface. Each pin's GPIO function can be independently enabled or disabled through the virtual port register operations, allowing selective activation of GPIO capabilities on pins that also serve peripheral functions, thus maintaining both peripheral reliability and GPIO versatility.
Data Source
AI summary
A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.