Virtual GPIO Power State Detection via Echo Retransmission

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Solution Overview

Problem

Conventional GPIO systems require multiple pins for IPC communication, leading to increased manufacturing costs and limited availability for other system-level interfaces, and existing solutions for power state blindness in interconnected devices involve additional hardware or latency-inducing protocols.

Innovation Solution

A virtual GPIO architecture with impedance-based flow control over a two-pin interface, allowing for multiplexed flow control and power state detection without additional pins or latency, using a loopback mechanism and unique message signatures to manage power state awareness and retransmissions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional GPIO systems are used for IPC communication, then reliable communication is achieved, but the number of pins required increases leading to higher manufacturing costs and limited availability for other interfaces

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidpin count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple GPIO signals into a single serialized transmission stream over one pin pair. The FSM (finite state machine) multiplexes multiple parallel GPIO signals onto a single serial channel, allowing N GPIO signals to be transmitted using only 2 physical pins (one for transmission, one for reception), thereby dramatically reducing the pin count while maintaining communication functionality

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent replaces the mechanical/electrical approach of using separate physical pins for each GPIO signal with a serial communication mechanism. Instead of requiring N separate physical connections, the system uses a single serial interface where signals are transmitted sequentially in time-multiplexed fashion, substituting physical connectivity with temporal multiplexing

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If additional flow control pins are added to manage power state blindness, then communication reliability improves, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvepower state detection reliabilityVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the existing transmit/receive pins perform multiple functions: they carry both the serialized GPIO data stream and the flow control signals. The same physical pins that transmit N GPIO signals also carry the flow control information, eliminating the need for separate dedicated flow control pins and reducing overall hardware complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent adds a temporal dimension to the communication protocol, using time-multiplexed transmission on the same physical channel for both data and flow control. Instead of using additional spatial resources (extra pins), the system multiplexes different signal types across time slots on the existing pin infrastructure

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Loss of information

If additional sideband signaling is used for power state awareness, then power state detection capability improves, but latency increases and device complexity grows

Engineering Contradiction:
Improvepower state informationVSAvoidcommunication latency
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent implements preliminary action by having the receiving device continuously monitor the serial channel for flow control signals even during what appears to be idle periods. When a transmit device needs to send data and the receive device is in a low-power state, the flow control mechanism allows the transmit device to wait or retry without requiring complex wake-up protocols, thereby reducing latency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses feedback through the flow control mechanism where the receive device sends signals back to the transmit device about its readiness state and power state conditions. This feedback loop allows the transmit device to adapt its transmission timing based on the receive device's actual state, eliminating the need for additional sideband signaling and reducing latency

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9971666B2Technique of link state detection and wakeup in power state oblivious interface
Publication Date: 2018.05.15 QUALCOMM INC
  • US9971666B2 patent drawing
  • US9971666B2 patent drawing
  • US9971666B2 patent drawing

AI summary

System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a bit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message. Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.