Virtual Ground Flash Memory Array With Shared Channel Layout
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Solution Overview
Problem
The complexity of configuring and forming split gate non-volatile flash memory cell architectures with multiple electrodes and channel regions makes it difficult to implement as critical dimensions shrink, leading to overly complex and challenging array layouts.
Innovation Solution
A memory device with a substrate featuring pairs of memory cells sharing a common erase gate and word line, with a continuous channel region extending between them, eliminating the need for a source region and select gate, and utilizing a virtual ground configuration to simplify the array layout and electrode connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If split gate non-volatile flash memory cells with multiple electrodes and separate channel regions are used, then memory cell functionality is achieved, but device complexity and array layout difficulty increase significantly
Solution Approach 1:
The patent merges two separate channel regions into a single shared channel region that serves both memory cells in a pair. This consolidation reduces the number of discrete components and simplifies the array layout while maintaining the necessary memory cell functionality through the shared channel structure.
Solution Approach 2:
The shared channel region performs multiple functions by serving as the channel for both memory cells in a pair simultaneously. This multi-functional design eliminates redundant structures and reduces overall device complexity while preserving full operational capability.
2Ease of operation
If multiple electrodes including source region and select gate are included for each memory cell, then complete memory cell operation is achieved, but manufacturing complexity increases
Solution Approach 1:
The invention combines the source region and select gate functions into a shared structure that serves both memory cells in a pair. This merging reduces the total number of electrodes that need to be manufactured and connected, thereby simplifying the manufacturing process while maintaining complete memory cell operation.
Solution Approach 2:
The patent extracts and eliminates redundant electrodes from the traditional split gate structure. By removing unnecessary duplicate components and retaining only the essential functional elements, the design reduces manufacturing complexity while preserving operational completeness.
3Area of moving object
If critical dimensions are reduced to increase storage density, then memory capacity increases, but configuration and forming of multiple electrodes becomes overly complex
Solution Approach 1:
By merging channel regions and sharing electrodes between paired memory cells, the invention reduces the number of discrete features that must be configured at reduced critical dimensions. This consolidation maintains storage density while avoiding the exponential increase in configuration complexity that would otherwise result from scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution simplifies the memory cell design and array layout, reducing complexity and improving erase efficiency by eliminating unnecessary electrodes and channel regions, while maintaining effective read and program operations through voltage coupling.
Implementation Method 1
utilizing a virtual ground configuration to simplify the array layout and electrode connections... while maintaining effective read and program operations through voltage coupling
Data Source
AI summary
A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.