Virtual HDBaseT Link Using Packet Timestamps for Clock Sync
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Solution Overview
Problem
HDBaseT data transmission over Ethernet networks faces challenges due to synchronization of different clock frequencies across network points, which is not supported by regular Ethernet switches, requiring specialized hardware like SyncE or IEEE 1588v2, which may not be available in many legacy networks.
Innovation Solution
A system and method to provide a virtual HDBaseT link using standard Ethernet switches without specialized hardware, by setting timestamp values in packets and calculating clock correction values to synchronize clocks and control data transmission, enabling clock synchronization and packet recovery over Ethernet networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If HDBaseT data is transmitted over standard Ethernet networks using regular switches, then device complexity and cost are reduced, but clock synchronization capability deteriorates
Solution Approach 1:
The patent introduces an intermediary mechanism (timestamping system and software-based synchronization protocol) that mediates between the HDBaseT data stream and the standard Ethernet switch infrastructure. This intermediary layer enables clock synchronization without requiring specialized hardware in the switches, thus maintaining device simplicity while achieving reliable synchronization.
Solution Approach 2:
The patent replaces the mechanical/hardware-based synchronization approach (SyncE requiring specialized switch hardware) with a software-based solution using timestamping and protocol-level synchronization. This substitution eliminates the need for specialized hardware while maintaining synchronization capability.
2Reliability
If specialized hardware like SyncE or IEEE 1588v2 is used for clock synchronization, then clock synchronization capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent employs lightweight timestamp values embedded in packet metadata rather than heavy specialized hardware components. These timestamp objects are simple, easily generated, and require minimal processing overhead, providing an economical alternative to expensive synchronization hardware.
Solution Approach 2:
The patent changes the synchronization approach from hardware-based clock signal manipulation to software-based timestamp parameter analysis. By measuring residence time through timestamp comparison and deriving frequency offset from these parameters, the system achieves synchronization through parameter calculation rather than hardware control.
3Measurement precision
If timestamp values are set for each packet to enable clock synchronization, then clock synchronization accuracy is improved, but processing time and complexity increase
Solution Approach 1:
The patent performs timestamp setting at the point of packet generation or ingress, which is a preliminary action that occurs naturally in the packet processing pipeline. This timing measurement is captured once at the source, eliminating the need for repeated measurements and reducing overall processing overhead.
Solution Approach 2:
The timestamping mechanism is integrated into the existing packet processing infrastructure, allowing the system to self-measure residence time without external intervention. The switches automatically capture timestamps using their existing clock sources, and the synchronization protocol itself provides the mechanism for calculating frequency offset, making the system self-sufficient.
Data Source
AI summary
Methods and systems for providing a virtual HDBaseT® link. In one embodiment, a first switch transmits packets over an Ethernet network that includes one or more hops. The payload of each of the packets includes an HDBaseT® T-packet belonging to an HDBaseT® session. A first processor sets, for each packet from among a plurality of the packets, a timestamp value in the packet to correspond to the time at which the packet is transmitted by the first switch. A second switch receives the packets over the Ethernet network. A second processor calculates a clock correction value based on the timestamps in the plurality of packets, and utilizes the clock correction value to perform at least one of the following: (i) control transmission, by the second switch, of data in T-packets in the payloads of the packets, and (ii) recover a source clock of native media delivered over the Ethernet network.