Virtual Hierarchy Floorplan for Electronic Design
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Solution Overview
Problem
Conventional electronic design methods face inefficiencies in manipulating hierarchies, particularly in creating and modifying cells and blocks, leading to pin or terminal misalignment and increased iterations, especially during prototyping and floorplanning stages, where existing IP cells or blocks are not available.
Innovation Solution
Implementing a floorplan with virtual hierarchies and figure groups allows for the creation of logical cells without manual pin or terminal identification, enabling manipulation and modification of cells as if they were physical, without the need to check out and check in physical cells, thus reducing computational overhead and iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional top-down or bottom-up approaches are used to manipulate hierarchies, then cells and blocks can be created and modified, but pin or terminal misalignment occurs and multiple iterations are required
Solution Approach 1:
The patent creates virtual copies of physical cells and blocks through virtual hierarchies. These virtual copies can be manipulated independently without affecting the physical database, allowing designers to experiment with different configurations, resize, reshape, and reorganize layout devices freely. The virtual hierarchy acts as a sandbox environment where multiple design iterations can be performed without repeatedly checking out and checking in physical cells, thus eliminating pin misalignment issues and reducing iteration time.
Solution Approach 2:
The patent introduces virtual hierarchies as an intermediary layer between the physical database and the design manipulation process. This intermediary virtual hierarchy absorbs the complexity of pin alignment and hierarchy manipulation, allowing designers to work with virtual copies while the system automatically manages the connection to physical cells. The virtual hierarchy mediates between design freedom and database consistency, preventing pin misalignment without constraining design iterations.
2Productivity
If physical cells are manipulated directly, then design changes can be made, but computational overhead increases due to frequent check out and check in operations
Solution Approach 1:
The patent creates virtual copies of physical cells and blocks that can be manipulated without triggering database check out/check in operations. These virtual copies reside in a virtual hierarchy that is computationally lighter to manipulate. Designers can perform multiple resize, reshape, and reorganization operations on virtual copies before committing any changes to the physical database, significantly reducing computational overhead and improving design manipulation efficiency.
Solution Approach 2:
The patent segments the hierarchy manipulation process into two distinct layers: virtual hierarchy manipulation and physical database updates. The virtual hierarchy layer handles frequent design explorations and iterations with minimal computational overhead, while the physical database layer is updated only when necessary. This segmentation isolates the computationally expensive check out/check in operations to rare events, thereby reducing overall computational resource consumption.
3Adaptability or versatility
If manual pin identification and creation is performed, then logical cells can be created, but the process becomes time-consuming and error-prone
Solution Approach 1:
The patent automatically copies pin and terminal information from physical cells to their virtual counterparts in the virtual hierarchy. This automatic copying eliminates the need for manual pin identification and creation, reducing errors and saving time. The virtual hierarchy inherits all necessary pin information from the physical database, allowing designers to create and manipulate logical cells with full adaptability without the tedious manual processes of conventional approaches.
Solution Approach 2:
The virtual hierarchy system performs self-service by automatically managing pin and terminal information. When a physical cell is instantiated in the virtual hierarchy, the system automatically creates corresponding virtual pins and terminals with correct identifications and connections. This self-service mechanism eliminates manual intervention, reducing both the time required and the potential for errors in logical cell creation while maintaining full flexibility.
Data Source
AI summary
Disclosed are methods, systems, and articles of manufacture for implementing a floorplan with virtual hierarchies and figure groups for an electronic design. These techniques identify a plurality of layout circuit component designs in a layout and identify or create a figure group at a virtual hierarchy for the plurality of layout circuit component designs. The figure group can be modified into a modified figure group in response to a request for a modification of the figure group. At least one layout circuit component design of the plurality of layout circuit component designs can then be reinstalled into the modified figure group to fulfill the request for modification of the figure group.