Virtual Interface System for Low Speed Bus Data Transfer
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Solution Overview
Problem
Traditional interfaces in computer technology face high interconnect costs and complex wire management due to multiple interfaces between the CPU and peripheral devices, leading to increased wire counts and software complexity.
Innovation Solution
A virtual interface system that implements a collection of interfaces on a master module and an actual collection of interfaces on a slave module, using a single wire for data transfer, which reduces signal complexity and eliminates the need for new drivers or code, while providing error protection and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple interfaces are connected directly between the CPU and each peripheral device, then data communication capability is improved, but wire count and interconnect complexity increase
Solution Approach 1:
The patent merges multiple individual interfaces into a single shared bus interface. Instead of having separate physical interfaces between the CPU and each peripheral device, the invention creates a common communication pathway where multiple devices can share the same physical connection, thereby reducing wire count while maintaining communication capability with all devices.
Solution Approach 2:
The shared bus interface is designed to be universal, capable of communicating with multiple different peripheral devices through the same physical connection. The interface can dynamically allocate communication resources to different devices as needed, making a single interface serve multiple functions that previously required multiple dedicated interfaces.
2Adaptability or versatility
If multiple interfaces are connected between the CPU and each component within a computer, then communication flexibility is improved, but software complexity increases
Solution Approach 1:
The patent introduces a bus arbitration mechanism as an intermediary that manages communication between the CPU and multiple peripheral devices. This arbitration layer handles the complexity of resource allocation, conflict resolution, and protocol management, thereby simplifying the software interface while maintaining flexible communication capabilities across multiple devices.
3Device complexity
If a shared bus interface is used to reduce wire count, then interconnect complexity is reduced, but data transfer speed decreases
Solution Approach 1:
The bus interface implements periodic time-division multiplexing, where communication with different peripheral devices occurs in alternating time slots. This periodic allocation of the shared bus to different devices allows for controlled data transfer rates that maintain acceptable speed performance while utilizing the simplified shared connection infrastructure.
Data Source
AI summary
Methods, apparatus, and systems for transferring data between a first and second module are provided. In one aspect, a method includes receiving, by a virtual controller register, outbound data; arbitrating, at a virtual arbitrate, the outbound data; transmitting, from the virtual controller register to the master low speed bus (LSB) frame/de-frame, the outbound data; adding, at the master LSB frame/de-frame, identification data to the outbound data to create an outbound data frame; transmitting, from the master LSB frame/de-frame to a slave LSB frame/de-frame, the outbound data frame; parsing, at the slave LSB frame/de-frame, the outbound data frame into parsed outbound data; arbitrating the parsed outbound data; transmitting, from the slave LSB frame/de-frame to the target controller register, the parsed outbound data; and receiving, at a target controller port from the target controller register, the parsed outbound data for transmitting to the slave device.