Virtual Interrupt Controller List Register Buffering

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Solution Overview

Problem

Existing data processing systems face performance issues in handling interrupts, particularly in real-time processing, due to the slow software-based virtual interrupt controller approach and the high hardware overhead of native hardware mechanisms, which impact overall system performance.

Innovation Solution

A hardware-based method for processing interrupt signals using virtual interfaces with list registers and interface registers to manage uncompleted interrupts, allowing for efficient interrupt processing and completion signaling without the full hardware overhead, leveraging a first control program to perform interrupt processing and a second control program for managing virtual interfaces and external interrupt controllers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a software-based virtual interrupt controller is used in the hypervisor code, then virtual machine interrupt processing is enabled, but interrupt processing speed deteriorates due to frequent hypervisor entries and simulated responses

Engineering Contradiction:

Improvevirtual machine interrupt processing capabilityVSAvoidinterrupt processing speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

A virtual interrupt controller is introduced as an intermediary component between the physical interrupt controller and virtual machines. This virtual interrupt controller operates in hardware mode with a list register to buffer interrupt requests, acting as a mediator that reduces direct hypervisor entries while maintaining virtual machine isolation and control over interrupt processing

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The virtual interrupt controller pre-processes interrupt requests by buffering them in a list register before actual processing. This preliminary action of collecting and preparing interrupt requests in advance reduces the frequency of hypervisor entries and enables more efficient interrupt handling for multiple virtual machines

Inventive Principle:

Principle #10Preliminary action

2Speed

If a hardware-based mechanism is used to support multiple virtual machines natively, then interrupt processing speed is improved, but hardware overhead increases and restrictions are imposed on the number of interrupts and virtual machines

Engineering Contradiction:

Improveinterrupt processing speedVSAvoidhardware overhead

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

Instead of implementing a complete hardware-based interrupt controller for each virtual machine, the invention uses a partial hardware approach with a single virtual interrupt controller that shares hardware resources. This partial action provides hardware-speed interrupt processing while avoiding the full hardware overhead and complexity of complete hardware isolation for each virtual machine

Inventive Principle:

Principle #16Partial or excessive action

3Productivity

If paravirtualisation with hypercalls is used, then interrupt overhead is reduced, but at least two hypervisor entries are still required for interrupt arrival and completion

Engineering Contradiction:

Improveinterrupt handling efficiencyVSAvoidhyperervisor entry overhead

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The virtual interrupt controller is designed to service itself by automatically buffering interrupt requests in its list register and generating virtual interrupts when ready. This self-service capability eliminates the need for continuous hypervisor intervention in interrupt routing, reducing hypervisor entry overhead while maintaining efficient interrupt handling

Inventive Principle:

Principle #25Self-service

Data Source

PatentEP2307972B1Interrupt control for virtual processing apparatus

Publication Date: 2012.12.19 ARM LTD

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AI summary

A data processing system supporting one or more virtual processing apparatuses is provided with external interrupt interface hardware (26) and virtual interface hardware (28). Hypervisor software responds to an interrupt received by the external interrupt interface hardware (26) to write data characterising that interrupt into list registers (18) of the virtual interface hardware (28). A guest operating system for the virtual machine of the virtual data processing apparatus being emulated may then read data from the virtual interface hardware (28) characterising the interrupt to be processed by that virtual machine. The virtual machine and the guest operating system interact with the virtual interface hardware (28) as if it were external interface hardware. The hypervisor software is responsible for maintaining the data within the virtual interface hardware (28) to properly reflect queued interrupts as received by the external interface (26).