Virtual Interrupt Routing via Hardware GIC Without VM-Exit
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Solution Overview
Problem
Existing interrupt handling processes in virtualization technologies involve delays due to the virtual machine monitor (VMM) triggering a VM-exit to write virtual interrupts into system registers, causing temporary suspension of virtual processors.
Innovation Solution
A system and method that utilize a hardware layer with a physical interrupt translation service (ITS) and a physical generic interrupt controller (GIC) to directly transfer virtual interrupt identifiers to target virtual processors without requiring the processors to exit, using preconfigured mapping relationships to ensure accurate interrupt handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the VMM writes the virtual interrupt into the system register corresponding to the virtual CPU by triggering VM-exit, then the virtual interrupt can be delivered to the virtual processor, but the virtual processor temporarily stops running and processing delay is increased
Solution Approach 1:
The patent introduces a hardware intermediary component (hardware interrupt controller) between the VMM and the virtual processor. This hardware layer receives virtual interrupt information from the VMM and directly delivers it to the virtual processor without requiring VM-exit, thereby eliminating the processing delay while ensuring reliable interrupt delivery.
Solution Approach 2:
The patent replaces the software-based interrupt delivery mechanism (relying on VM-exit and system register writes) with a hardware-based interrupt controller. This substitution eliminates the need for virtual processor suspension and enables direct hardware-level interrupt delivery, significantly reducing processing delay.
2Loss of time
If the VMM proactively triggers VM-exit to write virtual interrupt into system register, then the virtual interrupt can be written timely, but the virtual processor must temporarily exit and suspend execution
Solution Approach 1:
The hardware interrupt controller acts as an intermediary that receives virtual interrupt information from the VMM and directly delivers it to the virtual processor without requiring the processor to exit. This maintains both timely interrupt writing and continuous processor execution.
Solution Approach 2:
The patent replaces the software-based VM-exit mechanism with a hardware-based interrupt delivery system. The hardware interrupt controller can write virtual interrupt information into the virtual processor's register directly without suspending execution, thereby maintaining productivity while ensuring timely interrupt handling.
3Adaptability or versatility
If conventional software-based interrupt virtualization is used, then the system can provide virtual interrupt controller and translation service, but multiple processing steps are required and processing delay is increased
Solution Approach 1:
The patent replaces the software-based interrupt virtualization mechanism with a hardware-based solution. The hardware interrupt controller directly handles virtual interrupt translation and delivery, eliminating multiple software processing steps while maintaining interrupt virtualization capability. This reduces device complexity and processing delay.
Solution Approach 2:
The patent extracts the interrupt translation and delivery function from the software layer and implements it at the hardware level. By taking out these critical functions to the hardware layer, the system eliminates unnecessary software processing steps while preserving interrupt virtualization capabilities.
Data Source
AI summary
Embodiments of the present disclosure disclose a computing device, and are applied to the field of computing devices. In the present disclosure, a virtual interrupt obtained by a host machine is mapped to a physical interrupt of a physical layer, and a virtual interrupt identifier corresponding to the physical interrupt is transferred to a virtual processor by using the physical layer. When a hardware layer transparently transmits the virtual interrupt identifier to the virtual processor, the virtual processor does not need to exit. This decreases a delay caused by exit of the virtual processor when software implements virtual interrupt routing.


