Virtual I/O Queuing for FPGA Memory Optimization
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) have limited memory space to accommodate the large and deep I/O queues required for high-speed serial buses like PCI Express, which is a challenge for implementing high-performance non-volatile memory (NVM) systems.
Innovation Solution
The implementation of virtual I/O queuing using a state machine to manage a shared pool of buffers and queues, allowing for the exposure of logical block addresses and submission queues larger than what is physically implemented, enabling the use of NVMe protocol for NVM technology by dynamically managing Virtual Logical Block Addresses (VLBAs) and Virtual Submission Queues (VSQs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FPGAs implement large and deep I/O queues for high-speed serial buses, then system performance and parallelism are improved, but memory space requirements exceed available FPGA resources
Solution Approach 1:
The patent segments the I/O queue into multiple shallow queues distributed across different memory banks, rather than implementing a single deep queue. This allows the system to achieve equivalent total queue depth by parallelizing across multiple segments, fitting within limited FPGA memory while maintaining high I/O capacity.
Solution Approach 2:
The patent transitions from a single-dimension deep queue structure to a multi-dimensional array of shallow queues organized across multiple memory banks. By adding the memory bank dimension, the system achieves equivalent total queue depth without increasing the depth of individual queues, thereby fitting within available memory space.
2Ease of operation
If FPGAs allocate dedicated memory for each I/O queue, then queue management is simplified, but memory space is wasted due to fragmentation and cannot accommodate large queue depths
Solution Approach 1:
The patent merges multiple queue tail pointers and head pointers into shared memory locations that are multiplexed across different queues. Instead of dedicating separate memory space for each queue's control structures, the system combines these control elements and time-multiplexes them, reducing overall memory usage while maintaining manageable queue operations.
Solution Approach 2:
The patent implements universal memory structures that serve multiple queues simultaneously. The same memory banks and control logic are shared across multiple I/O queues, allowing the system to manage many queues with a unified memory management approach rather than requiring dedicated memory for each queue.
3Adaptability or versatility
If FPGAs implement virtualization to expose logical block address spaces larger than physical implementation, then adaptability to emerging NVM technologies is improved, but device complexity increases
Solution Approach 1:
The patent introduces a translation layer that acts as an intermediary between the host's logical block addresses and the physical memory addresses in the FPGA. This translation mechanism, implemented through configurable address translation logic, allows the system to support larger logical address spaces than physically available while managing the complexity through a dedicated translation subsystem.
Solution Approach 2:
The patent employs configurable address translation parameters and mapping relationships that can be dynamically adjusted to support different NVM technologies and address space requirements. By making the translation parameters configurable rather than fixed, the system adapts to emerging technologies without requiring fundamental redesigns.
Data Source
AI summary
One or more virtual functions are exposed via a shared communication interface. Memory across said virtual functions is shared to provide a fixed number of I/O buffers shared across said virtual functions. For each of said one or more virtual functions, storing a corresponding map table configured to store a mapping data that maps a logical block address of the virtual function to a corresponding allocated one of said fixed number of I/O buffers based at least in part on a current state of a state machine.