Virtual I/O Queueing for FPGA Memory Constraints
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) have limited memory space to accommodate the large and deep I/O queues required for high-speed serial buses like PCI Express, which are essential for high-performance storage systems using non-volatile memory (NVM) media.
Innovation Solution
The implementation of virtual I/O queueing using a state machine to manage a shared pool of buffers and queues, allowing for the exposure of logical block addresses and submission queues larger than what is physically implemented on the FPGA, enabling the use of protocols like NVMe for NVM technology by dynamically managing Virtual Logical Block Addresses (VLBAs) and Virtual Submission Queues (VSQs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If FPGAs use traditional physical I/O queue implementation, then memory space requirements are met, but the ability to support large and deep I/O queues required for high-speed serial buses like PCI Express is limited
Solution Approach 1:
The patent creates virtual copies of I/O queues through software abstraction layers. Instead of physically implementing every queue in hardware, the system creates virtual representations that can be managed dynamically. This allows the FPGA to support more queues than physical memory would normally allow by using software-based queue management and mapping techniques.
Solution Approach 2:
The patent transitions from a single-dimension physical memory implementation to a multi-dimensional virtual address space. By introducing virtual addressing, the system can map a large logical address space to a smaller physical memory space, enabling support for large and deep I/O queues without proportionally increasing physical memory requirements.
2Productivity
If FPGAs implement large numbers of deep I/O queues in hardware, then PCI Express requirements are met, but FPGA memory resources are exhausted
Solution Approach 1:
The patent implements dynamic queue management where the number and depth of I/O queues can be adjusted at runtime based on actual workload requirements. Instead of statically allocating fixed memory resources for queues, the system dynamically allocates and deallocates queue resources, allowing high throughput when needed while conserving memory resources during lower-demand periods.
Solution Approach 2:
The patent creates a universal queue management system that can handle multiple types of I/O operations across different protocols and applications using a shared pool of memory resources. The virtualized queue infrastructure provides multi-functional capability, allowing the same physical memory to serve multiple logical queues with different requirements.
3Ease of operation
If FPGAs allocate dedicated memory for each I/O queue, then queue isolation and management are simplified, but memory efficiency decreases
Solution Approach 1:
The patent merges multiple individual queue memories into a single shared memory pool that serves all I/O queues. Instead of having separate dedicated memory regions for each queue, the system combines them into one unified resource that is dynamically allocated to different queues as needed. This maintains management simplicity through unified control while dramatically improving memory utilization efficiency.
Solution Approach 2:
The patent introduces a virtualization layer as an intermediary between the physical memory and the I/O queues. This intermediary manages the mapping between virtual queue addresses and physical memory locations, providing simplified queue management interfaces to applications while efficiently utilizing underlying physical memory resources through sophisticated allocation algorithms.
Data Source
AI summary
One or more virtual functions is exposed via a shared communication interface. A plurality of I/O buffers shared across said virtual functions are provided. For each of said one or more virtual functions, a corresponding submission queue comprising one or more virtual submission queue entries (SQEs) is used, wherein a memory access device is configured to: receive data pushed to the memory access device by a client host system, store the data in an allocated one of the I/O buffers, receive a submission queue entry (SQE) that invokes one of said virtual functions with respect to the data, and use a corresponding one of the plurality of logic circuits that is associated with the invoked virtual function to perform the virtual function with respect to the data as stored in the allocated I/O buffer.