Virtual Lock Step Device Data Correction for Memory Failures
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Solution Overview
Problem
Conventional adaptive double device data correction (ADDDC) technologies face inefficiencies in handling multiple memory failures, leading to reduced error-correcting performance and increased server downtime due to inflexible region register management and excessive occupation of backup memory spaces.
Innovation Solution
Implementing a dynamic bank virtual lock step (VLS) technique that utilizes a modified region register with bank group information to manage multiple memory failures dynamically, allowing for flexible bank-level and rank-level VLS operations, thereby extending the system's ability to handle more failures without occupying all backup memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ADDDC technology is used to handle memory failures, then basic error correction is provided, but the system cannot handle multiple failures effectively and backup memory spaces are excessively occupied
Solution Approach 1:
The patent implements dynamic bank virtual lock step (VLS) that adapts its behavior based on failure patterns. The system dynamically determines whether to activate bank-level VLS, rank-level VLS, or both, depending on the distribution and severity of memory failures. This dynamic adaptation allows the system to handle multiple failures effectively while optimizing backup memory space utilization.
Solution Approach 2:
The patent segments the memory correction process into two independent levels: bank-level VLS and rank-level VLS. Each level can be activated independently based on failure characteristics. Bank-level VLS handles failures within specific banks, while rank-level VLS handles failures across entire ranks. This segmentation enables flexible combination to address multiple failure scenarios without excessive backup occupation.
2Ease of operation
If bank-level virtual lock step is used to correct memory failures, then failures within specific banks are handled, but failures spanning multiple banks require additional rank-level intervention
Solution Approach 1:
The correction mechanism is segmented into two independent levels: bank-level VLS for handling failures within specific banks, and rank-level VLS for handling failures spanning multiple banks. Each level operates with its own logic and can be activated independently, making the complex multi-level correction manageable through modular design.
Solution Approach 2:
Both bank-level and rank-level VLS mechanisms serve universal purposes by providing virtual lock step correction capabilities. The rank-level mechanism extends the bank-level functionality to handle cross-bank failures, making the system universally applicable to various failure patterns without requiring separate dedicated mechanisms for each scenario.
3Reliability
If region registers are used to manage backup memory spaces, then failure recovery is enabled, but the registers become occupied by backup spaces reducing available correction capacity
Solution Approach 1:
The patent changes the parameter of backup memory space utilization by implementing selective VLS activation. Instead of reserving all backup spaces, the system activates bank-level VLS for minor failures and rank-level VLS only when necessary, changing the effective backup space parameter dynamically based on failure severity and distribution.
Solution Approach 2:
The patent applies local quality by providing different levels of backup protection based on local failure conditions. Bank-level VLS provides localized protection for failures in specific banks, while rank-level VLS provides broader protection only when failures span multiple banks. This localized approach reduces overall backup space occupation while maintaining adequate protection.
Data Source
AI summary
An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to identify failed memory regions in a memory by a rank, bank, and device associated with the failed memory region, and provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory. Other embodiments are disclosed and claimed.