Virtual Memory Devices with Demultiplexer Register for Energy Efficiency
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Solution Overview
Problem
Current memory modules are energy inefficient due to excessive activation of bits during memory access, with many bits being accessed and stored without being used, especially in multi-core systems where independent memory access requests from multiple threads lead to inefficient energy usage.
Innovation Solution
The introduction of multi-core memory modules with virtual memory devices (VMDs) and a demultiplexer register that allows separate memory requests to be sent to each VMD, reducing the number of memory chips involved per access and minimizing unnecessary bit activation through time-division multiplexing and command-specific routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple memory chips are activated simultaneously to increase memory bandwidth and capacity, then memory performance is improved, but energy consumption increases due to excessive bit activation
Solution Approach 1:
The memory module is divided into multiple independently controllable virtual memory devices (VMDs), each corresponding to a specific memory chip. This segmentation allows the memory controller to activate only the specific VMD needed for a given memory access, rather than activating all memory chips simultaneously. The demultiplexer register routes commands to specific VMDs based on the access pattern, reducing unnecessary bit activation and associated energy consumption while maintaining high bandwidth through parallel independent accesses.
2Reliability
If all memory chips are activated for each access to ensure data availability, then reliability is improved, but energy efficiency deteriorates due to wasted power on unused bits
Solution Approach 1:
Each virtual memory device is associated with a specific memory chip and has independent control over its activation. The memory controller can selectively activate only the local VMD that contains the required data, rather than activating all VMDs. This local quality approach ensures data availability for the specific access pattern while avoiding the energy waste of activating and storing data in unused memory chips and bits.
3Productivity
If memory accesses from multiple threads are interleaved to improve throughput, then productivity is improved, but device complexity increases due to independent control requirements
Solution Approach 1:
The demultiplexer register serves as an intermediary component between the memory controller and the virtual memory devices. It receives commands from the memory controller and routes them to the appropriate VMD based on the access pattern. This intermediary simplifies the control architecture by providing a centralized command distribution mechanism, enabling efficient thread interleaving and high throughput without proportionally increasing control complexity.
Data Source
AI summary
Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module (500) includes at least one virtual memory device and a demultiplexer register (502) disposed between the at least one virtual memory device and a memory controller. The demultiplexer register receives a command identifying one of the at least one virtual memory devices from the memory controller and sends the command to the identified virtual memory device. In addition, the at least one virtual memory devices include at least one memory chip.