Virtual Memory Fragment-Aware Cache for Page Table Entry Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current virtual memory systems face challenges in achieving high cache hit rates due to fixed page sizes and dictated page table entry formats, which lead to latency and inefficiencies in memory access, especially in multitasking systems with multiple subsystems accessing physical memory.
Innovation Solution
A virtual memory fragment-aware cache is introduced, where page table entries are organized into fragments with specific sizes and alignment boundaries, allowing for parallel cache banks to store page table entries and improve cache hit rates by dynamically mapping logical to physical memory addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If fixed page sizes and dictated page table entry formats are used, then system compatibility and ease of operation are improved, but cache hit rates deteriorate and memory access latency increases
Solution Approach 1:
The patent segments page table entries into fragments organized by contiguous virtual page ranges with identical physical page mappings. This fragmentation allows the cache to store only unique mapping relationships rather than every individual page table entry, significantly increasing cache hit rates while maintaining fixed page size compatibility.
Solution Approach 2:
The system performs preliminary organization of page table entries into fragments before cache lookup. By pre-grouping entries with identical physical mappings into contiguous virtual page ranges, the system prepares the data structure to maximize cache efficiency without changing the fundamental fixed page size architecture.
2Reliability
If all page table entries are stored in cache, then cache hit rates are improved, but memory access time and device complexity worsen
Solution Approach 1:
The patent divides the page table into fragments where each fragment contains multiple page table entries that map contiguous virtual pages to the same physical pages. The cache stores these fragmented representations rather than complete page table entries, reducing cache memory requirements and access time while maintaining high hit rates through intelligent fragmentation.
Solution Approach 2:
The system transitions from storing page table entries in a traditional linear fashion to organizing them by contiguous virtual page ranges with identical physical mappings. This dimensional reorganization allows the cache to represent multiple page table entries through a single fragmented entry, reducing cache access time and complexity.
3Device complexity
If traditional page table translation is used, then system simplicity is improved, but performance and productivity deteriorate due to latency
Solution Approach 1:
The system performs preliminary organization of page table entries into fragments during system initialization or page table updates. This pre-processing groups entries with identical physical mappings into contiguous virtual page ranges, so that during runtime, cache lookups can efficiently retrieve fragmented representations that cover multiple page table entries, significantly improving memory access performance without complicating the translation mechanism.
Solution Approach 2:
The patent introduces dynamic fragmentation where page table entries are organized into fragments based on contiguous virtual page ranges with identical physical mappings. This dynamic organization adapts to the actual memory access patterns and page table structure, improving performance by caching only unique mapping relationships while maintaining system simplicity through standard cache mechanisms.
Data Source
AI summary
The present invention is directed to a method, computer program product, and system for processing memory access requests. The method includes the following features. First, page table entries of a page table are organized into at least one fragment that maps logical memory to at least one of logical memory or physical memory. The at least one fragment has a fragment size and an alignment boundary. Then, a subset of the page table entries stored in one of a plurality of cache banks is accessed to determine a mapping between a first logical memory address and at least one of a second logical memory address or a physical memory address. Each cache bank is configured to store at least one page table entry corresponding to a fragment of a predetermined set of fragment sizes and a predetermined alignment boundary.