Virtual Memory Manager for Heterogeneous DRAM and NAND Flash
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Solution Overview
Problem
Current storage class memory systems face challenges in efficiently managing data across heterogeneous memory devices, particularly in balancing access frequency and endurance profiles between low-latency DRAM and higher-latency NAND flash memory, leading to wear issues and inefficient data placement.
Innovation Solution
Implementing a virtual memory manager that tracks access counts for data structures across multiple memory devices, moving less frequently accessed or updated data to lower-level memory devices with higher latency and greater endurance, while keeping frequently accessed data in low-latency DRAM, and using wear leveling techniques to distribute write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data structures are stored in low-latency DRAM (first level memory device), then access speed is improved, but memory capacity is limited and cost increases
Solution Approach 1:
The memory system is segmented into multiple levels: DRAM for frequently accessed data structures and NAND flash for less frequently accessed data structures. This segmentation allows the system to provide fast access for critical data while maintaining large capacity for bulk storage, resolving the contradiction between speed and capacity.
Solution Approach 2:
The patent introduces a hierarchical dimension to memory organization, moving from a single-level memory structure to a multi-level hierarchy. Data structures are placed in different memory levels based on access frequency, creating a dimensional approach that simultaneously optimizes for both speed (DRAM layer) and capacity (NAND flash layer).
2Quantity of substance
If data structures are stored in high-capacity NAND flash memory (second level memory device), then storage capacity is improved and cost is reduced, but access latency increases
Solution Approach 1:
The system dynamically manages data structure placement between DRAM and NAND flash based on access counts and usage patterns. Frequently accessed data structures are automatically moved to or kept in DRAM, while less frequently accessed ones are moved to NAND flash. This dynamic management ensures that capacity-efficient NAND flash storage does not sacrifice necessary access speed for active data.
3Productivity
If write operations are concentrated on specific flash memory cells, then write speed is improved, but cell endurance is reduced due to limited erase cycles
Solution Approach 1:
The patent extracts the wear problem from the storage system by implementing a log-structured file system that separates active data structures from the main storage pool. New writes are appended to a log area rather than overwriting existing cells, and periodic garbage collection redistributes data across available cells. This extraction of write operations to dedicated areas and redistribution mechanisms prevents any single cell from exhausting its erase cycles, maintaining reliability while preserving write performance.
Data Source
AI summary
Provided are a computer program product, system, and method for maintaining data structures in a virtual memory comprised of a plurality of heterogeneous memory devices. Access counts are maintained for a plurality of data structures stored in a first level memory device. A determination is made of data structures in the first level memory device having lowest access counts. The determined data structures are deleted from the first level memory device and retaining copies of the data structures in a second level memory device, wherein the first level memory device has lower latency than the second level memory device.