Virtual Memory Mapping for Cross-Device Data Transfer Latency

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing methods for data transfer between CPUs and external devices like GPUs introduce latency and memory inefficiencies due to redundant data copies across user and kernel space boundaries, and often require customized hardware or complex device driver development.

Innovation Solution

The method involves mapping virtual memory addresses to physical addresses with kernel permissions, allowing data to be received and copied between devices while minimizing redundant copies by using existing kernel APIs, thereby reducing latency and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If data is transferred between devices using traditional kernel buffer methods, then data transfer can be performed, but redundant data copies are created and latency increases

Engineering Contradiction:
Improvedata transfer latencyVSAvoidredundant data copies
Core Design Contradiction:
Loss of timeVSLoss of substance

Solution Approach 1:

The patent merges the user-space buffer and kernel-space buffer into a single shared buffer in kernel space. The CPU and GPU both access the same physical memory region, eliminating the need for separate buffers and the redundant copying operations between them. This is achieved through the CPU accessing the shared kernel buffer directly via virtual memory mapping, while the GPU accesses it through DMA.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a shared kernel buffer as an intermediary memory region that mediates data transfer between CPU and GPU. Instead of copying data through multiple intermediate buffers, both devices access this single intermediary buffer, reducing the number of copy operations and associated latency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If customized hardware support is used to avoid redundant copies, then data transfer efficiency improves, but hardware compatibility and adaptability decrease

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidhardware compatibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal data transfer mechanism that works with standard hardware interfaces and existing kernel APIs. By using general-purpose virtual memory mapping and standard DMA operations rather than device-specific customized hardware, the solution maintains compatibility with various CPUs, GPUs, and DMA controllers while still achieving efficient single-buffer data transfer.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of substance

If device-specific collaboration is used during driver development, then redundant copies are avoided, but device driver complexity and development cost increase

Engineering Contradiction:
Improveredundant data copiesVSAvoiddevice driver complexity
Core Design Contradiction:
Loss of substanceVSDevice complexity

Solution Approach 1:

The patent segments the data transfer functionality into distinct components: virtual memory mapping for CPU access, DMA configuration for GPU access, and shared buffer management. This segmentation allows each component to be implemented using existing standard APIs and mechanisms, reducing the need for complex custom device driver development while still eliminating redundant copies.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9436395B2Mechanisms to save user/kernel copy for cross device communications
Publication Date: 2016.09.06 ADVANCED MICRO DEVICES INC
  • US9436395B2 patent drawing
  • US9436395B2 patent drawing
  • US9436395B2 patent drawing

AI summary

Central processing units (CPUs) in computing systems manage graphics processing units (GPUs), network processors, security co-processors, and other data heavy devices as buffered peripherals using device drivers. Unfortunately, as a result of large and latency-sensitive data transfers between CPUs and these external devices, and memory partitioned into kernel-access and user-access spaces, these schemes to manage peripherals may introduce latency and memory use inefficiencies. Proposed are schemes to reduce latency and redundant memory copies using virtual to physical page remapping while maintaining user/kernel level access abstractions.