Virtual Memory Mapping for DRAM Page Locality
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Solution Overview
Problem
Existing systems fail to effectively improve DRAM locality for contiguous virtual memory pages accessed in close proximity, leading to increased memory latency and communication overhead due to non-contiguous mapping of virtual memory pages to physical memory pages.
Innovation Solution
A method that analyzes memory-bound accesses to determine contiguity between virtual memory pages and maps sets of these pages to single physical memory pages, optimizing DRAM locality by predicting and modifying mappings based on access patterns, cost-benefit analysis, and properties like write intensity and temporal proximity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If contiguous virtual memory pages are mapped to non-contiguous physical memory pages, then virtual address space can be non-contiguous and fragmentation is hidden, but DRAM locality deteriorates and memory access latency increases
Solution Approach 1:
The system performs preliminary analysis of memory access patterns to identify contiguity between virtual memory pages before mapping them to physical memory. By predicting which virtual pages will be accessed contiguously and pre-establishing their mapping to contiguous physical pages, the system optimizes DRAM locality before actual access occurs, reducing memory access latency while maintaining virtual address flexibility
Solution Approach 2:
The mapping relationship between virtual and physical memory pages is made dynamic rather than static. The system continuously monitors memory access patterns and adjusts the mapping of virtual pages to physical pages based on observed contiguity. This dynamic adaptation allows the system to optimize for DRAM locality when contiguity is detected while maintaining the ability to handle non-contiguous access patterns when needed
2Device complexity
If virtual memory pages are mapped to physical memory pages without analyzing access patterns, then system complexity is reduced, but DRAM locality deteriorates and processor cycle consumption increases
Solution Approach 1:
Instead of analyzing all virtual memory pages uniformly, the system applies partial action by focusing analysis only on those pages that exhibit contiguity in access patterns. The system performs detailed access pattern analysis selectively on candidate pages where contiguity is detected, rather than applying complex analysis to the entire virtual address space, thus balancing system complexity with productivity optimization
3Device complexity
If large-scale pages (superpages) are mapped to maintain translation simplicity, then address translation complexity is reduced, but DRAM locality optimization is lost
Solution Approach 1:
The system segments the virtual address space into smaller units of analysis, examining contiguity at the level of individual virtual pages or small groups of pages rather than requiring large superpage mappings. This segmentation allows the system to identify and optimize contiguous access patterns at a finer granularity, improving DRAM locality without requiring the complexity of managing large superpage translations
Data Source
AI summary
Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.