Virtual Memory Address Mapping in Programmable Logic
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Solution Overview
Problem
The challenge in programmable integrated circuits (ICs) is efficiently mapping and routing memory access requests from a programmable logic sub-system to the physical memory addresses corresponding to program variables, especially when using virtual memory addresses, which can lead to increased software complexity and reduced portability.
Innovation Solution
A system comprising a processing sub-system and a programmable logic sub-system, where the programmable logic sub-system includes a memory management circuit to map virtual memory addresses to physical addresses and translation look-aside buffers (TLBs) to determine and cache physical memory addresses for efficient memory access, allowing the programmable logic to access variables directly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If virtual memory addresses are used by the processing sub-system, then software portability and memory management flexibility are improved, but the complexity of mapping virtual addresses to physical addresses increases
Solution Approach 1:
The patent introduces translation look-aside buffers (TLBs) as intermediary hardware structures between the processing sub-system and memory management circuit. These TLBs cache virtual-to-physical address mappings, allowing the programmable logic sub-system to access memory efficiently without requiring complex real-time address translation for each memory access request.
Solution Approach 2:
The memory management circuit performs address mapping in advance by pre-loading virtual-to-physical address translations into the TLBs. This preliminary action allows the programmable logic sub-system to directly access cached physical addresses without undergoing complex address translation during runtime operations.
2Speed
If the programmable logic sub-system directly accesses memory using virtual addresses, then access speed is improved, but the memory management circuit becomes overloaded
Solution Approach 1:
The TLBs serve as an intermediary caching structure that relieves the memory management circuit from handling every memory access request. The TLBs store pre-computed physical addresses corresponding to virtual addresses, allowing fast direct access while distributing the mapping burden away from the memory management circuit.
Solution Approach 2:
The system creates a copy of the address mapping information by replicating virtual-to-physical address translations in the TLBs. This copying allows multiple components to access the same mapping data simultaneously without overloading the original memory management circuit, enabling parallel memory access operations.
3Productivity
If translation look-aside buffers are introduced to cache address mappings, then memory access efficiency is improved, but hardware complexity increases
Solution Approach 1:
The TLBs are implemented as universal caching structures that can be configured to handle different addressing modes and memory access patterns. These buffers serve multiple functions including virtual-to-physical address translation caching, memory access acceleration, and support for both processing sub-system and programmable logic sub-system operations.
Data Source
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AI summary
A processing sub-system (1 10/412) is configured to execute a program using a set of virtual memory addresses to reference memory locations for storage of variables of the program. A programmable logic sub-system (120/420)is configured to implement a set of I/O circuits (124/126/426/428) specified in a configuration data stream, each of the I/O circuits (124/126/426/428) having a respective ID and configured to access one of the variables. A memory management circuit (170/470) is configured to map the virtual memory addresses to physical memory addresses of a memory and map IDs to the physical address used to store the corresponding variables. A TLB (144/146/442/444/446) is configured to receive a memory access request, from the I/O circuits (124/126/426/428), each request indicating an ID and provide, to the memory, a memory access request indicating the physical memory address that is mapped to the ID.