Virtual Memory Circuit Encoding Page Size for Unified TLB Translation

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Solution Overview

Problem

Existing CPU architectures face inefficiencies with 4 KB pages in large virtual address spaces, leading to increased TLB misses, energy consumption, and complexity due to multiple page sizes requiring separate L1 TLBs and hardware page table walkers.

Innovation Solution

A method and system for encoding virtual memory addresses with settable bitfields to implicitly encode page size and using a one-level page table for efficient translation, eliminating the need for multiple L1 TLBs and hardware page table walkers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If 4 KB pages are used in large virtual address spaces, then memory management granularity is improved, but TLB miss rate increases and performance deteriorates

Engineering Contradiction:

Improvememory management granularityVSAvoidaddress translation performance

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent implements dynamic page size selection where the system can choose between 4 KB and large pages (e.g., 1 GB) based on workload characteristics. The MMU and OS work together to dynamically allocate appropriate page sizes, allowing small pages for fine-grained management when needed and large pages for contiguous memory access patterns, thereby optimizing both granularity and performance

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If multiple page sizes are supported, then memory management flexibility is improved, but device complexity increases due to separate L1 TLBs and hardware page table walkers

Engineering Contradiction:

Improvememory management flexibilityVSAvoidTLB and page table walker complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a unified L1 TLB design that can handle multiple page sizes (4 KB and large pages) through a single data structure. The TLB uses virtual address and page size as indices to retrieve physical address translations, eliminating the need for separate TLB structures for different page sizes while maintaining full functionality for both page types

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the functionality of separate L1 TLBs for different page sizes into a single unified TLB structure. Instead of having distinct TLB instances for 4 KB and large pages, the system combines them into one TLB that uses composite indexing (virtual address + page size) to achieve the same translation capability with reduced hardware complexity

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If multiple L1 TLBs and hardware page table walkers are implemented, then address translation capability is improved, but energy consumption increases

Engineering Contradiction:

Improveaddress translation capabilityVSAvoidenergy consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent combines multiple L1 TLBs and hardware page table walkers into a unified structure. The single L1 TLB handles translations for all page sizes, and the unified hardware page table walker manages large page translations, reducing the total number of active translation components and thereby lowering energy consumption while maintaining full address translation capability

Inventive Principle:

Principle #5Merging (Combining)

4Device complexity

If a one-level page table is used, then device complexity is reduced, but virtual address space capacity is limited

Engineering Contradiction:

Improvepage table structure complexityVSAvoidvirtual address space capacity

Core Design Contradiction:

Device complexityVSArea of stationary object

Solution Approach 1:

The patent changes the parameters of the one-level page table by allowing variable page sizes (4 KB and large pages). By using large pages (e.g., 1 GB), the system can map larger virtual address spaces with fewer page table entries, effectively expanding the addressable space while maintaining the simplicity of a one-level structure. The page size parameter becomes a key factor in determining the mapping capacity

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12443540B1Virtual memory circuit with virtual address encoding

Publication Date: 2025.10.14 KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS

AI summary

A virtual memory system for managing a virtual memory page table for a central processing unit and a system of encoding a virtual address (VA) is disclosed. The system includes a memory storing an encoded virtual address, a virtual page number having a settable bitfield that is set according to page size and offset, and a virtual memory. The virtual memory addressing circuitry is configured with a zero detector logic circuit and a virtual page number (VPN) multiplexer. The zero detector logic circuit is configured to read bits of the encoded virtual address and outputs the page size. The virtual page number (VPN) multiplexer is configured to select the virtual page number based on the page size and outputs an index to a page table.