Virtual Memory Circuit for Multi-Size Page Table Selection
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Solution Overview
Problem
Modern CPU architectures face inefficiencies and increased energy consumption due to the use of multiple page sizes in virtual memory systems, which complicate TLB implementation and require complex hardware solutions for address translation.
Innovation Solution
A method and system for encoding virtual memory addresses with multiple page sizes using a one-level page table and a virtual memory system that includes a Zero Detector logic circuit and a VPN multiplexer to simplify address translation, reducing the need for multiple L1 TLBs and hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple page sizes are supported in virtual memory systems, then the system can efficiently manage different memory allocation requirements, but the TLB implementation becomes complex and energy consumption increases
Solution Approach 1:
The patent implements a universal TLB design where a single TLB structure handles multiple page sizes (4KB, 64KB, 16MB, 4GB) through configurable entry formats. The TLB uses a unified search mechanism that can interpret virtual addresses with different page size encodings, eliminating the need for separate TLB instances for each page size while maintaining full compatibility with diverse memory allocation requirements.
Solution Approach 2:
The patent changes the parameters of TLB entries to accommodate multiple page sizes by using variable-length page number fields and offset fields. The TLB entry format includes configurable bits that indicate page size, allowing the same hardware structure to adapt its behavior based on the detected page size parameter. This enables dynamic parameter adjustment without requiring multiple fixed-structure TLBs.
2Adaptability or versatility
If multiple page sizes are supported in virtual memory systems, then the system can efficiently manage different memory allocation requirements, but energy consumption increases
Solution Approach 1:
The patent merges the functionality of multiple page size handlers into a single unified TLB structure. Instead of having separate TLBs for 4KB, 64KB, 16MB, and 4GB pages that would each consume power independently, the patent combines them into one shared resource. The unified TLB uses a single search logic and comparison circuitry that processes all page sizes, significantly reducing the overall energy consumption while maintaining support for diverse page sizes.
Solution Approach 2:
The universal TLB design performs multiple functions (handling different page sizes) within a single energy-consuming hardware block. This multi-functionality eliminates redundant energy consumption that would occur with separate dedicated TLBs for each page size, as the same comparison and search circuits are reused across all page size types.
3Device complexity
If a one-level page table is used with encoded virtual addresses, then TLB implementation is simplified and energy consumption is reduced, but the ability to handle large virtual address spaces may be limited
Solution Approach 1:
The patent extends the virtual address space capacity by utilizing additional bits in the encoded virtual address format. The system supports up to 61-bit virtual addresses by incorporating extended page number fields and appropriate offset fields in the TLB entry structure. This dimensional extension allows the one-level page table approach to handle vastly larger address spaces that would traditionally require multi-level page tables.
Solution Approach 2:
The patent changes the parameters of the TLB entry structure to accommodate 61-bit virtual addresses. The TLB entries include configurable page number fields that can hold up to 61 bits of virtual address information, along with corresponding offset fields. This parameter adjustment enables the simplified one-level page table to maintain the capability to address large virtual memory spaces without requiring complex hierarchical structures.
4Device complexity
If hardware page table walkers and MMU caches are eliminated, then device complexity and energy consumption are reduced, but address translation performance may be impacted
Solution Approach 1:
The patent uses preliminary action by pre-loading frequently accessed page table entries into the TLB before they are needed. The system maintains a unified TLB that is proactively updated with translation entries, reducing the need for on-demand page table walking. This preliminary caching of translation information in the simplified hardware structure maintains fast address translation performance while eliminating the need for complex hardware page table walkers.
Solution Approach 2:
The patent uses copying by replicating essential page table entry information in the unified TLB structure. Instead of having separate hardware page table walkers that would traverse multi-level page tables, the system copies relevant translation information into the TLB in advance. This copying approach allows the simplified hardware to achieve fast translation speeds without requiring the complex walking logic of traditional multi-level page table implementations.
Data Source
AI summary
A virtual memory system for managing a virtual memory page table for a central processing unit and a system of encoding a virtual address (VA) is disclosed. The system includes a memory storing an encoded virtual address, a virtual page number having a settable bitfield that is set according to page size and offset, and a virtual memory. The virtual memory addressing circuitry is configured with a zero detector logic circuit and a virtual page number (VPN) multiplexer. The zero detector logic circuit is configured to read bits of the encoded virtual address and outputs the page size. The virtual page number (VPN) multiplexer is configured to select the virtual page number based on the page size and outputs an index to a page table.