Virtual Memory Paging Mechanism for TLB Performance
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Solution Overview
Problem
Current computer systems face inefficiencies in translation lookaside buffer (TLB) performance due to limited page size options, which result in increased TLB miss rates and reduced effective capacity, while also requiring support for legacy paging modes to run existing software.
Innovation Solution
The processor introduces a virtual memory paging mechanism that enables the use of multiple page sizes, including superpages formed by contiguous 4 KB pages, allowing a single virtual address to access a region of memory, and includes a translation lookaside buffer (TLB) that interprets a single entry as referring to a superpage when a superpage enable indicator is asserted, supporting both host and guest operating systems in virtualized environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the TLB uses fixed page sizes (4 KB, 2 MB, 1 GB), then the system maintains compatibility with existing architectures, but the TLB capacity and coverage are insufficient leading to increased miss rates
Solution Approach 1:
The patent segments the TLB entry into two parts: a standard page table entry for compatibility and a superpage indicator bit. This allows the TLB to effectively represent larger pages (64 KB, 256 KB, 1 MB) by combining multiple standard pages while maintaining the existing TLB structure and entry format, thus increasing capacity without changing the fundamental TLB architecture
Solution Approach 2:
The patent introduces dynamic page size support by enabling the TLB to interpret entries differently based on the superpage indicator bit. The same TLB entry can represent different page sizes (standard or superpage) depending on the indicator, allowing flexible adaptation to different memory access patterns and workloads without hardware changes
2Productivity
If larger page sizes are used to increase TLB coverage, then TLB miss rate decreases, but memory allocation efficiency deteriorates for applications that do not require large data sets
Solution Approach 1:
The system dynamically selects between standard pages and superpages based on the actual memory access patterns and workload requirements. The superpage indicator bit allows the processor to treat a TLB entry as a superpage only when beneficial, maintaining the ability to use smaller pages for applications that don't benefit from larger pages, thus preserving memory allocation efficiency
Solution Approach 2:
The patent changes the effective page size parameter dynamically by introducing the superpage indicator bit. This allows the system to vary the page size parameter from standard sizes to larger superpage sizes (64 KB, 256 KB, 1 MB) depending on the specific memory access patterns, optimizing both TLB performance and memory utilization
3Productivity
If new page sizes are introduced to improve TLB performance, then system performance increases, but compatibility with legacy software deteriorates
Solution Approach 1:
The patent makes the TLB entry universal by adding a superpage indicator bit that can be either set or cleared. When cleared, the entry behaves as a standard page for legacy compatibility. When set, it functions as a superpage for performance enhancement. This multi-functionality allows the same TLB entry structure to serve both legacy and enhanced modes
Solution Approach 2:
The superpage indicator bit acts as an intermediary between the legacy TLB structure and the enhanced superpage functionality. It provides a backward-compatible interface that allows new superpage features to be introduced without breaking existing software, as the indicator bit can be ignored by legacy systems while enabling enhanced performance when needed
Data Source
AI summary
A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted.