Virtual Memory Region Mapping for Storage Device Performance
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Solution Overview
Problem
The complexity and cost of designing systems that utilize different types of memory, such as volatile DRAM and nonvolatile NAND flash memory, for embedded systems, due to their distinct functionalities and requirements, lead to increased design complexity and manufacturing costs.
Innovation Solution
An electronic system with a host device and a storage device that includes a volatile memory device and a nonvolatile memory device, where the storage device provides a virtual memory region by mapping a host-dedicated memory region of a smaller size to a larger virtual memory region, using a memory-mapped input-output interface and a block accessible interface, with a virtual memory controller managing dynamic and static mapping tables to optimize access and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different types of memory (DRAM and NAND flash) are used for their distinct functionalities, then system performance and data storage capabilities are improved, but design complexity and manufacturing cost increase
Solution Approach 1:
The patent combines DRAM and NAND flash memory into a single storage device with a unified interface. The controller integrates multiple functions including memory management, data buffering, and flash translation layer capabilities, allowing the system to access both volatile and non-volatile memory through a single interface rather than requiring separate interfaces for each memory type.
Solution Approach 2:
The unified interface designed in the patent serves multiple purposes: it can address DRAM regions for high-speed access, access NAND flash blocks for mass storage, and manage data transfers between the two memory types. This multi-functional interface reduces the need for separate control logic and simplifies system architecture.
2Reliability
If different types of memory (DRAM and NAND flash) are used for their distinct functionalities, then system performance and data storage capabilities are improved, but manufacturing cost increases
Solution Approach 1:
By merging DRAM and NAND flash into a single storage device with a unified interface, the patent reduces the total component count in the system. Instead of requiring separate memory modules and their associated control circuits, the unified design consolidates these functions into one device, thereby reducing assembly complexity and manufacturing cost.
3Quantity of substance
If a virtual memory region is provided by mapping a smaller host-dedicated memory region to a larger virtual memory space, then memory space efficiency is improved, but access complexity increases
Solution Approach 1:
The patent introduces a virtual memory region as an intermediary layer between the host interface and the physical memory structures. This virtual region acts as a buffer that abstracts the complexity of data distribution across DRAM and NAND flash, allowing the host to access a large contiguous memory space without needing to understand the underlying fragmented physical structure.
Solution Approach 2:
The patent adds a virtualization dimension to the memory architecture. By creating a virtual memory space that is larger than the physical host-dedicated memory region, the system enables addressing of NAND flash blocks through byte-addressable virtual addresses, effectively adding an addressing dimension that simplifies host access to block-based storage.
Data Source
AI summary
An electronic system includes a host device and a storage device including a first memory device of a volatile type and a second memory device of a nonvolatile type. The first memory device is accessed by the host device through a memory-mapped input-output interface and the second memory device is accessed by the host device through a block accessible interface. The storage device provides a virtual memory region to the host device such that a host-dedicated memory region having a first size included in the first memory device is mapped to the virtual memory region having a second size larger than the first size.