Virtual Memory Mapping via Sub-Block Allocation
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Solution Overview
Problem
Conventional computer systems waste memory and restrict minimum allocation size due to fixed page sizes, leading to suboptimal memory usage and complexity in managing memory across different types of memory.
Innovation Solution
Implementing a memory management system that allows virtual addresses to map to sub-blocks of memory smaller than the processor's page size, enabling efficient allocation and management of smaller memory chunks, and allowing multiple virtual addresses to map to a single physical block, thereby optimizing memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If fixed page size allocation is used to maintain application transparency, then application simplicity is preserved, but memory waste increases and minimum allocation is restricted to page size
Solution Approach 1:
The patent divides a physical memory page into multiple sub-blocks (e.g., 512-byte sub-blocks within a 4KB page). The memory control layer can allocate individual sub-blocks to applications rather than entire pages, reducing memory waste while maintaining application transparency through virtual address mapping.
Solution Approach 2:
The patent introduces a new dimension of granularity between page and byte levels by creating sub-blocks. This intermediate level allows precise memory allocation (e.g., 512 bytes) without requiring full page allocation (4KB), resolving the contradiction between transparency and waste.
2Ease of operation
If fixed page size allocation is used, then application transparency is maintained, but minimum allocated block size is restricted to page size
Solution Approach 1:
By segmenting pages into sub-blocks, the system enables flexible allocation sizes (e.g., 512 bytes, 1KB, 2KB) while maintaining page-level transparency for applications. The memory control layer handles sub-block management invisibly to applications.
Solution Approach 2:
The system dynamically allocates sub-blocks of varying sizes within pages based on application needs. The memory control layer can allocate different sub-block sizes (512 bytes, 1KB, etc.) from the same physical page to different applications, providing adaptability while maintaining transparency.
3Productivity
If applications manage data movement between memory types, then memory usage can be optimized, but application complexity increases
Solution Approach 1:
The memory control layer acts as an intermediary between applications and physical memory. It transparently manages data movement between fast and slow memory types, allowing applications to use simple virtual addresses while the intermediary optimizes memory usage efficiency.
Solution Approach 2:
The memory control layer autonomously manages memory allocation, mapping, and data movement without application intervention. Applications simply request memory using virtual addresses, and the system self-manages the complex tasks of allocating sub-blocks and moving data between memory types.
4Productivity
If applications have global view of memory need, then memory allocation can be optimized, but memory management becomes non-transparent to applications
Solution Approach 1:
The memory control layer serves as a global intermediary that has visibility of all memory needs across applications. It optimizes allocation by allocating sub-blocks from the same physical page to multiple applications, achieving global optimization while maintaining transparency through virtual address mapping.
Solution Approach 2:
The memory control layer provides universal management for all applications, handling allocation, mapping, and data movement for multiple applications simultaneously. It can allocate sub-blocks from shared physical pages to multiple applications, achieving global optimization while each application experiences simple, transparent access.
Data Source
AI summary
A processor (e.g. utilizing an operating system and/or circuitry) may access physical memory by paging, where a page is the smallest partition of memory mapped by the processor from a virtual address to a physical address. An application program executing on the processor addresses a virtual address space so that the application program may be unaware of physical memory paging mechanisms. A memory control layer manages physical memory space in units of sub-blocks, wherein a sub-blocks is smaller than a size of the page. Multiple virtual address blocks may be mapped to the same physical page in memory. A sub-block can be moved from a page (e.g. from one physical memory to a second physical memory) without moving other sub-blocks within the page in a manner that is transparent to the application program.