Virtual Metrology Model for Wafer Result Prediction

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Solution Overview

Problem

Traditional virtual metrology (VM) models in semiconductor fabrication are time-consuming, lack interpretability, and often provide inaccurate predictions due to reliance on statistical methods without domain knowledge, leading to inefficient process control and inadequate root cause analysis during excursion events.

Innovation Solution

A method that integrates domain knowledge into the determination and selection of predictor parameters, removes collinearity, and builds VM models using regression analysis to predict wafer results and analyze excursion events, ensuring high accuracy and interpretability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional statistical methods are used to build VM models, then the models can be constructed, but the predictions are inaccurate and lack interpretability

Engineering Contradiction:
Improveprediction accuracyVSAvoidmodel interpretability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent transforms the modeling approach by changing from pure statistical methods to domain knowledge-guided parameter selection. Predictor parameters are carefully selected based on semiconductor process understanding, and interaction terms are explicitly defined to represent physical relationships, thereby improving both accuracy and interpretability simultaneously

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces domain knowledge as an intermediary between raw process data and the VM model. Expert knowledge about semiconductor manufacturing processes guides the selection of predictor parameters and the formulation of interaction terms, acting as a mediator that ensures the model reflects physical reality while maintaining interpretability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If many predictor parameters are used in the VM model, then prediction coverage is improved, but model complexity increases and computation time increases

Engineering Contradiction:
Improveprediction accuracyVSAvoidmodel complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts only the most relevant predictor parameters based on domain knowledge of semiconductor processes. By selectively taking out and including only those parameters that have proven impact on wafer results, the model achieves high prediction accuracy without unnecessary complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the predictor parameters into meaningful groups based on their functional relationships in the semiconductor manufacturing process. This segmentation allows for systematic selection of key parameters and their interactions, reducing the overall model complexity while maintaining comprehensive coverage

Inventive Principle:
Principle #1Segmentation

3Reliability

If traditional VM models are used, then process control can be performed, but root cause analysis during excursion events is inadequate

Engineering Contradiction:
Improveprocess control capabilityVSAvoidroot cause information
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent incorporates feedback mechanisms where the VM model continuously monitors process parameters and compares predicted versus actual wafer results. During excursion events, this feedback loop enables systematic analysis of which predictor parameters deviated from expected values, providing actionable root cause information for process control improvements

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12112107B2Virtual metrology for wafer result prediction
Publication Date: 2024.10.08 TOKYO ELECTRON LTD
  • US12112107B2 patent drawing
  • US12112107B2 patent drawing
  • US12112107B2 patent drawing

AI summary

Aspects of the disclosure provide a method for wafer result prediction. The method includes determining predictor parameters of a semiconductor process using domain knowledge that includes knowledge of the semiconductor process, a processing tool associated with the semiconductor process, a metrology tool, and/or the wafer. The method also includes removing collinearity among the predictor parameters to obtain key predictor parameters, and selecting a subset of the key predictor parameters based on metrology data of the wafer obtained from the metrology tool. The method further includes building a virtual metrology (VM) model on the subset of the key predictor parameters and may include predicting wafer results using the VM model.